You can refer to the code examples that comes with PSoC Creator. I believe the DMA_UART_PSoC4 code example is the closest to what you want to do.
I have investigated the Shift Register component if it is fit to the DMA.
The Shift Register component requires following two steps to send a word from the Shift_Out pin.
- Write 24-bit data to the FIFO as the ShiftReg_WriteData(uint32 shiftData) API function doing.
- Give a pulse to the "Load" pin.
In the first step the FIFO status is checked in the API function before writing a new word to the FIFO. When using the DMA to this step the DMA will write a word without checking the FIFO status because there is no output to notify the FIFO status as a hardware signal.
There is no suitable component to generate a pulse as the second step. In addition there is no output to notify the shift operation completed. An external logic is required to count the shift clock and generate a Load signal every 24 clocks.
As the result of the investigation, I think that the Shift Register component is not suitable for the DMA implementation. It is better to make a new 24-bit shift register component made for DMA.
By the way, is it available to use an SPI instead of the shift register? I think it is better to use an SPI component mated with a DMA to generate a serial stream output.
If you want the DMA to be triggered by the FIFO status, you can easily modify the ShitReg component to output that.
The SPI is also a good way to do this.
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Check these older threads for RAM-DMA-ShiftReg examples
Please tell me/us what you mean by easily modifying the shiftreg component. external logic, change the UDB, rewrite the verilog code....
I am way too much of a newby to "make a new 24-bit shift register component made for DMA".
However, please tell me how you came to the conclusion that the shiftregister component can not be made to work with DMA.
Your investigation statements of conclusion are not backed up with helpful facts or reference material with those helpful facts. The shiftreg data sheet says quite clearly that it can be used with DMA and I was/am prepared to create some external logic to facilitate the effort... but I need facts.
thanks and regards
I assumed that the system will be as following diagram. The ShiftRegControl (sequencer) block must be prepared by a user.
The sequence is as follows.
- At first, the DMA is configured to be armed and the ShiftReg has no data.
- A software trigger starts a SHIFT sequence by any method. This may be invoked as an API function of the sequencer.
- The sequencer waits for the ShiftRegister's FIFO is empty by the "fifo_empty" signal.
- The sequencer triggers the DMA by the dma_trigger signal.
- The DMA starts a 3-bytes of transfer from RAM to ShiftReg.
- When the transfer ends, the sequencer is notified by the end_of_dma signal.
- The sequencer waits for the ShiftRegister's shift operation is completed.
- The sequencer triggers the load_trigger signal to load the 3-bytes data from the FIFO to Shift Register.
- The ShiftReg automatically starts 24-bit shift operation.
- Go to step 3 for next transfer until all data are transferred.
This scenario is available if the Shift Register component has the "end_of_shift" and "fifo_empty" status signals. These signals can be added by modifying the Shift Register component. But there is no such a component right now.
Above scenario is caring the status of the Shift Register too much. It depends on the system if any status can be neglected.
You can modify the ShiftReg component to add a new terminal, like fifo_tx_status. Link this terminal to a signal in the Verilog code generated by the datapath module. The FIFO status is one of the output signals from the datapath, called f0_blk_stat().
I think you could simply configure your DMA to trigger on LEVEL and connect the trigger input to the status of the FIFO. There is no need to use the LOAD signal. As long the FIFO is not FULL, you can trigger the DMA to write in the FIFO.
Is the shift register NOT deterministic? If set to 24 bit shifting, does it not complete the shift by the 25th rising edge of the clock after the load signal happens? Clearly, I have not thought this all the way to a solution.... However, if the "ShiftRegControl" is a LUT type of state machine, and is clocked by the "Clock_Shifter", don't we know enough about the shift register component to know when to load the next 24 bits from the DMA?
If that is all true-ish, my next question is this: The DMA component seems to be set up for 8, 16 or 32 bit transfers. Do I run it as a 32 bit device when moving 24 bit words into the shift register? OR, do I do 3 (8 bit) transfers (more for the LUT type of state machine to keep track of)?
My impression of the DMA configurations is that:
One word per tr_in signal is doable, my LUT type of state machine could keep track of the loads to the shift register and it can also notice when the DMA data is at its end (via the tr_out signal).
Thank you for your thoughts
You see how much of a newby I am by my other posts. I am very interested in learning data path stuff, verilog stuff as well as UDB and component editing. While we are exchanging comments (and I am not in the deep end yet), would you share a few tips on how to get insight into existing components like the shift register? Can you just open a file while in Creator and see verilog "scripts" or tables?
thanks very much
You can refer to the following video:
Once you import the ShiftReg, there is a Verilog code that you can modify it.
OKAY>>>> I have not tried this yet, but, tr_out is a 41ns pulse that happens when a transfer from memory to the shift register (if the transfer mode is set to single element per transfer. So, to use it as an input to my LUT, I need to stretch it.... (with a SRflipflop and async preset).
My LUT outputs need to:
activate tr_in on the DMA 1st....on count 0
then, activate load on the shift register.....on count 1
count 8 clock rising edges of the Shift_Clock.....AND as long as DMA data elements remains, repeat
Let me try this much and see what else I discover.