4 Replies Latest reply on Nov 14, 2014 5:49 PM by userc_6396 Branched from an earlier discussion.

    BCM2073X GPIO Explained

      Yes, BCM20737S is used.

      Just to mention, to avoid confusion: you find also a datasheet for BCM20737, not with S. On first look it seems to be similar, but it is not. If you check pins, GPIO ports etc. - go with the BCM20737S, this is the one which matches with schematic (a SoM, not an SoC).

       

      My question:
      In FW I see code like this:

       

      // If timed wake is enabled, clear P39 interrupt if waking from timed wake.

          gpio_clearPinInterruptStatus(GPIO_PIN_P39 / GPIO_MAX_NUM_PINS_PER_PORT, GPIO_PIN_P39 % GPIO_MAX_NUM_PINS_PER_PORT);

       

      and:

      // Disable GPIOs double bonded with the ones we plan to use in this app.

          gpio_configurePin((GPIO_PIN_P10) / 16, (GPIO_PIN_P10) % 16, GPIO_INPUT_DISABLE, 0);

       

      But I have no clue what P39 and P10 is: I cannot find these in datasheet.

      Does anybody know what it will do and if it is correct? (if not available on HW - what happens if code tries to do?)


      The gpiodriver.h defines really GPIO_PIN_P0 ... GPIO_PIN_P39 and GPIO_NUM_PINS = GPIO_NUMBER_OF_PINS is really set to 40 (0..39). Hard to find, but comes via make command line, set in file Wiced-Smart/spar/spar_2037x.inc .

        • 1. Re: WICED Sense confusion
          MichaelF_56

          Because the BCM2073X device exists in multiple packages, the firmware is designed to use a series of logical pins that can map to whatever physical pins are available on the SOC package being used.

           

          The logical pins that are available for GPIO are listed in the SIP Module datasheet and the HW Interfaces guide which are both available in the community site.

           

          Because these map through a mux matrix inside to the SIP module to the physical pins on the SOC was is internal to the module, reading through the firmware code can be confusing to anyone that does not know the internal mapping.

          • 2. Re: WICED Sense confusion

            Sorry, I'd like to ask again:

            What is P10 and P39 ?

             

            Sure, yes, I know (familiar with pinmux and writing generic code for different chips and versions).
            But still not clear: even the BCM20737 datasheet does not have P10 or P39. So, it looks to me the code is doing something which is secret (hidden to us) or not correct (maybe coming from other chips, older versions).
            My concerns are:

            • I want to understand the code - really every line - if needed: what is it doing, what is it used for.
              Here, I do not find what P10 and P39 are. (even the comments do not tell me anything to get a clue).
            • If we write code for a chip, even we reuse code, we should not do invalid actions, invalid configs. Some chips are sensitive: if you access a register which might exist in chip A but same code running on chip B where this register is not there (or has different feature) - it can hang (or do something strange, fire a bus trap etc.).
            • If I see in datasheet:
              "The following GPIOs are available:
              - P0 - P4
              - ...
              - P32"
              and I count - it ends up in 14 available GPIOs (mentioned in block diagram, figure 1). And P10, P39 are not mentioned in this list (in both datasheets).

            But the value in project is set to 40 GPIOs which does not match with datasheet. 39 I could understand (P0..P38), but 40? (14 would be even more correct in C-code)
            And changing this value in make file to a matching 39 will break compile because P39 is used without any #ifdef around.
            #ifdef's would help also to see differences on chips, same code for different platforms or chips and obvious which code is valid for what. But using a non-existing P39 ... 
            (STM FW would be a good example for such approach)

            • 3. Re: WICED Sense confusion
              ArvindS_76

              The 2073x chip (die) has 40 logical GPIOs (P0-P39). The 32 pin package (the SoC - 20736 and 20737 *without* the S) only brings out 14 of those. The System in Package (the 20736S and 20737S modules) follow the SoC very closely in which pins are brought out (but there is a slight difference) and these are what you see in the datasheets. There are other packages that bring out more/all pins. Since the 32 pin package (SoC) and the modules are pin-limited, some of the logical GPIOs are multi-bonded before bringing them out on the balls on the chip. For the 32 pin package, the following are bonded:

               

              P8 and P33

              P10, P11, P27 and 32 KHz xtal in

              P12, P26 and 32 KHz xtal out

              P13 and P28

              P14 and P38

               

              See the SiP module datasheet for the bonding information on the S modules.

               

              You can use only one of the GPIOs (or its alternate function) from each of the rows above. The other unused GPIO from that should in general be input/output disabled (especially when it is an input).

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              • 4. Re: WICED Sense confusion

                Thank you, I got it as:
                it does not harm to enable, disable or even write to these GPIOs which are not bonded (and coming out).
                They do not have any function. Right?
                Now it sounds fine by me (actually I would remove such code then).