2 Replies Latest reply on Sep 27, 2017 7:09 AM by 18540759_2777766

    Fastest binary sampling frequency possible on PSoc 5LP

    18540759_2777766

      I'm using the PSoC 5LP on the CY8CKIT-059 development board for a segment of my final year engineering project. I need to sample binary data at the highest frequency possible. I'm currently using a 50% DC PWM to generate a stream of 1's and 0's as dummy data of a set frequency. I would like to know the minimum sampling period achievable. For the real system the data is not a PWM stream, but an external binary (0 V or 5 V) signal from an IR receiver at a constant frequency. And the faster I can sample, the faster I can transmit my data to the board. I'm using the clock set-up at 78 MHz

       

      I can currently sample one bit every 1.038 us. I do this as follows:

      I set up the PWM to create an interrupt at any edge. In the main, when the dummy data starts being received (PWM start), the PWM pin (my "receiver") interrupt is triggered. This enables a flag, which when caught in the main, disables the PWM pin ("receiver") interrupt. Thereafter I enable a timer set for half the PWM period, which sets a sample flag at each interrupt. Each time this sample flag is set, I read the pin by performing a read function on the PWM pin and store it into an array. I have tried other methods, but this is around the fastest speed I could achieve as of yet. Is there anyway of getting a smaller sampling period?  I would preferably like to be able to sample data at every 50, 100, or 200 ns, but anything better than what I have is already an improvement.

       

      Excuse me if this is a really stupid question, but I don't have much experience with this processor. I can attach a minimal project if necessary. Also, if I left out any other details, I will gladly provide them if you let me know.

       

      Thanks in advance. Any help would be greatly appreciated.

       

      Message was edited by: Marcel Stegmann