I dont understand your project.
In main, everything is commented out, except spis_start().
thats the point...
the project includes a SPI Master that read out a Accelleration IC. Everything for this is commented out, so that the Psoc dont do anything.
The only active part is the SPI Slave that should send the accelleration data to the raspberry pi.
The problem is, that the SPI Slave send data without using "SPIS_1_WriteTxData"... even when i use "SPIS_1_ClearTxBuffer()"
This problem you see in the screenshot of the oscilloskop. The main programm does nothing... but the slave sends 0x33...
A 2MHz clock is provided to the Clock input of the SPI Slave component.
The Clock input is used to sample the input signals to the SPI Slave component such as MOSI, SCK, and SS. In the configuration tool, it was described that the "Bit Rate" is "1/2 Input Clock Frequency" In this case the maximum bit rate is set to 1MHz. 2MHz SPI signal cannot be accepted.
Please provide more fast clock like 4MHz to the Clock input.
Thank you for your answer... But i dont think i have to choose 4MHz or faster... Because than this example of cypress wouldn't make sense...
My main question is, why the psoc sends everytime the last byte i put in the TxBuffer... Like you see in the screenshot. Even when i dont put anything in the TxBuffer... the Psoc keeps on sending 0x33, even after clearing the TxBuffer or Clear the Fifo...
Should the psoc dont send 0x00 when there is nothing in the TxBuffer?
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I understand the point.
This is caused by the internal structure of SPI.
When calling the SPIS_ClearTxBuffer() the FIFO state is cleared but the FIFO contents are not cleared. Following comes from the "PSoC® 5LP Architecture TRM (Technical Reference Manual) Document No. 001-78426."
In addition the TX interrupt is disabled.
SPIS_1_txBufferFull = 0u; /* If Buffer is empty then disable TX FIFO status interrupt */ SPIS_1_TX_STATUS_MASK_REG &= (uint8)~SPIS_1_STS_TX_FIFO_NOT_FULL; /* Enable Interrupt. */ SPIS_1_EnableTxInt();
The TX interrupt will be caused when FIFO is not FULL and used to fill a byte of written data. So when TX interrupt is disabled no data will be filled to the FIFO and the empty FIFO returns the last byte unless filling. As the result SPI will pull the LAST DATA from the empty FIFO and send the LAST BYTE every time. It seems that the LAST BYTE after the reset sequence is 0x33.
I understand... Thank you
So, a solution could be something like:
Interrupt when Fifo is empty -> Write 0x00 to TxBuffer
And when i want to send Data:
Clear Fifo and fill with my own Data
So, everytime my own Data are send out ( Fifo empty ) the Fifo would be filled with 0x00.