2 Replies Latest reply on Sep 27, 2017 11:44 PM by user_246598725

    PSoC Warp Verilog: signed reg / signed wire

    user_246598725

      Hi,

       

      I'm fighting with a Verilog implementation which should be configurable to work with either signed or unsigned parallel input. The Warp Verilog reference guide states that reg vectors can be signed. For wire vectors, it's not explicitely mentioned that they can't be of signed value.

      PSoC Creator throws the error message 'Syntax error at/before reserved symbol 'signed'.' This let me assume that having signed wires is not possible. If this is true, it would be nice if this error message could be more precise about that.

       

      Anyway, if wire vectors can't be signed, how can I solve the problem? I can try to implement it with signed reg vectors, but wouldn't that cost more ressources?

       

      Regards,

       

      Ralf