Can you share the screen shot of random data that you have sent and received data?
Also let us know the size of the data you have sent over OUT End point and size of data you requested to received on IN Endpoint?
Can you probe the data lines over the GPIF Interface and check whether the FPGA is Looping back the data correctly?
What it is send to FPGA and what FPGA is looped back?
You can also do copying the 1024 packet that is send over BULK OUT EP to local buffer and print it over the UART Interface. For this, we have to use DMA manual channel,
and copy the DMA Buffer to a local buffer in the DMA PRODUCER Event Call back (CY_U3P_DMA_CB_PROD_EVENT).
Do the same for the buffer received on GPIF Side and print it over the UART.
This helps in understanding where it is going wrong either in FX3 or FPGA.
Is the same happening at 100 MHz too?
Can you share the schematic of FX3 part?
Please check whether you have followed Hard ware guidelines provided in the AN70707 App Note.
Especially, GPIF Part
We also found that the data was correct at 50MHz and 60MHz, while the average speed is 15MB/s approximately.