It is true as the CY7C1049GN datasheet said that VOH(min)=4.0V at IOH=-0.1mA
Please note that this is guaranteed by design and not tested.
By the way, IOH=-0.1mA is enough to drive the data bus?
The minimum capacitance of an output pin is COUT=10pF and the bus will be driven from 0V to 4V. The rising time is calculated by
It is too big comparing to the required access speed 80ns.
Does this condition satisfy your requirement?
Yes, IOH=-0.1mA is enough to drive the data bus!
For me, the read cycle time is not important.
I forgot to write, that one write cycle should not last more than 80ns.
I think with the CY7C1049GN its not a problem, because the write cycle time in the datasheet is indicated with twc=10ns.
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Go ahead and use CY7C1049GN devices for 5V legacy systems.
As Noriaki mentioned, these devices can support VOH of upto Vcc-0.5V and thats something we have tested during characterization.
One correction about rise time, this device is a 10ns device, so its very much capable of performing 10-14 ns cycles (as your board load conditions might vary, you have to have some margin)
But I see that the cycle times you are targeting is 80ns, so this should not be a problem.
Have you considered using Micropower SRAMs? The cycle time requirement is 45-50ns and they have very low power consumption
(CY62147G is an example device)