3 Replies Latest reply on Oct 11, 2017 8:42 AM by nile

    Fast asynchronous SRAM output HIGH voltage problem

    andreas.raffl1_2769856

      Hi,

       

      For my application I need a fast asynchronous single port SRAM(organisation: 8bit x32k to 512k x8bit; speed: time<80ns) , which I would  supply with 5V. The min. Output HIGH voltage of the SRAM must be higher than 3,25V.

      In this application note (http://www.cypress.com/file/38176/download ) I have found two different RAMs(CY7C199CN, CY7C1049BN), that would  theoretically  fit for my case, because these are devices from the older generation( 250nm & 350nm technologie). According to this application note, these SRAMs should have an Output HIGH Voltage VOH, which is  5V TTL compatible.

      But after I have read the ratings from the datasheet, I was a bit confused because there is written a min. Output HIGH Voltage of  VOH=2,4V.

      Is the minimum output HIGH voltage VOH>3,25V, if the chip(CY7C199CN or CY7C1049BN or CY7C1049GN) is supplied with Vcc=5V and the output HIGH current (IOH)is  very low (µA)?

       

      It’s true that, according to the ratings in the CY7C1049GN datasheet Vcc=min=4,5V, and the minimal Output HIGH Voltage VOH is more than Vcc-0,5V=4,5V-0,5V=4V?

       

      Or do there exist other SRAM that would be suitable for my application?

       

      The datasheets and the application note you can find in the attachment!

       

      Sorry for my English…

      Thanks!

      Best regards

        • 1. Re: Fast asynchronous SRAM output HIGH voltage problem
          ntan

          It is true as the CY7C1049GN datasheet said that VOH(min)=4.0V at IOH=-0.1mA

          Please note that this is guaranteed by design and not tested.

           

          By the way, IOH=-0.1mA is enough to drive the data bus?

          The minimum capacitance of an output pin is COUT=10pF and the bus will be driven from 0V to 4V.  The rising time is calculated by

           

          tR=COUT*VOH(min)/IOH=400ns

           

          It is too big comparing to the required access speed 80ns.

          Does this condition satisfy your requirement?

           

          Regards,

          Noriaki

          • 2. Re: Fast asynchronous SRAM output HIGH voltage problem
            andreas.raffl1_2769856

            Yes, IOH=-0.1mA is enough to drive the data bus!

             

            For me, the read cycle time is not important.

            I forgot to write, that one write cycle should not last more than 80ns.

            I think with the CY7C1049GN its not a problem, because the write cycle time in the datasheet is indicated with twc=10ns.

             

             

             

             

            Best regards

            • 3. Re: Fast asynchronous SRAM output HIGH voltage problem
              nile

              Andreas,

              Go ahead and use CY7C1049GN devices for 5V legacy systems.

              As Noriaki mentioned, these devices can support VOH of upto Vcc-0.5V and thats something we have tested during characterization.

               

              One correction about rise time, this device is a 10ns device, so its very much capable of performing 10-14 ns cycles (as your board load conditions might vary, you have to have some margin)

              But I see that the cycle times you are targeting is 80ns, so this should not be a problem.

               

              Have you considered using Micropower SRAMs? The cycle time requirement is 45-50ns and they have very low power consumption

              (CY62147G is an example device)

               

              Regards,

              Nilesh