The switching of states in GPIF occurs almost instantaneously.
Now, in Synchronous mode, DR_GPIO signal is driven after 2 clock cycles when early mode is selected and 3 clock cycles when Delayed mode is selected.
In the first logic analyser capture, you can observe that signal D0 is asserted/de-asserted two cycles after LV is asserted/de-asserted.
I suppose, D1 is configured in Delayed mode leading to a 3-cycle latency.
PUSH_DATA_SCK1 will be capturing the correct data and there will be no unknown state as such between state transitions.