5 Replies Latest reply on Sep 15, 2017 5:41 AM by jowac_2717596

    CX3: Raised PCLK at GPIF II


      in the "HowToInterfaceMIPI.pdf" document you say that the maximum supported PCLK is 100 MHz.

      We have a raw12 data format with 4 data lanes and maximum data rate of 400Mbit/s at each lane transferred using the CSI2 interface.

      Is it possible to configure the MIPI CSI2 controller so that we can transmit our data in parallel over the GPIFII interface using a bus width of 24bit?


      Thanks in advance!