-
1. Re: FX3 EP0 write/read delay?
raghuramh_86 Sep 5, 2017 8:55 AM (in response to milkfish1227_2635671)Hi,
What is the buffer size (ul_len) you have set? How many bytes are you sending from FX3 to PC in a single Control transfer?
-
2. Re: FX3 EP0 write/read delay?
milkfish1227_2635671 Sep 5, 2017 9:24 AM (in response to raghuramh_86)Buffer size in PC 256 uint8. I am sending 4 byte data in a EP0 control transfer.
In FX3, buffer was 4096. I changed to 256, doesn't seems make any difference. FX3 just loopback 4 byte data received from EP0.
//uint8_t glEp0Buffer[4096] __attribute__ ((aligned (32)));
uint8_t glEp0Buffer[256] __attribute__ ((aligned (32)));
-
3. Re: FX3 EP0 write/read delay?
milkfish1227_2635671 Sep 6, 2017 2:10 PM (in response to milkfish1227_2635671)Hi,
Do we have any Cypress tech support/engineer can help?
Thanks,
Dick
-
4. Re: FX3 EP0 write/read delay?
madhul_36 Sep 10, 2017 8:30 PM (in response to milkfish1227_2635671)Hi Dick Lin,
From the other post, I see that you are actually doing SPI Transfer inside the setup callback. In order to narrow down the issue, please remove the SPI Transfer part of the code and see how much time it takes.
Regards,
- Madhu Sudhan
-
5. Re: FX3 EP0 write/read delay?
milkfish1227_2635671 Sep 11, 2017 9:27 AM (in response to milkfish1227_2635671)I already comment out the SPI transition. The only thing the switch case doing is get EP0 data and send EP0 data. See below.
I have another post titled "
EP0 Read() takes 5 seconds to complete.
" has the source code for both host and FX3 firmware.
case CY_FX_RQT_SPI_FLASH_WRITE:
status = CyU3PUsbGetEP0Data (wLength, glEp0Buffer, NULL);
// if (status == CY_U3P_SUCCESS)
// {
// status = CyFxSpiTransfer (wIndex, wLength, glEp0Buffer, CyFalse);
// }
// for testing
status = CyU3PUsbSendEP0Data (wLength, glEp0Buffer);
break;