3 Replies Latest reply on Feb 10, 2018 5:24 AM by user_148813134

    Current consumption too high in sleep mode after migration to another device


      We migrated our design from a PSoC Cy8C3246 to a Cy8C3466 and moved some pins in the PCB in order to optimize our hardware design for the analog parts. Now we see that the total current consumption during sleep () is elevated from 8µA in the original design to a variable range from 200µA to 1200µA.  In order to be able to pinpoint the source of this current, we've built a dummy project configuring all pins in the proper mode and level acoording to the hardware design. We use a sleep mode with a 1PPS wakeup timer. The proper functioning of the sleep function is monitored using the uart_putchar() function. All hardware pins have been measured with an oscilloscope  in order to detect unaccounted signal levels . Internally no devices other than the uart  for debugging purposes and all hardware pins are defined in the TopDesign level. Even removing some components from the PCB did not solve the problem. Furthermore, the problem is found in all tested devices of our production batch. We suspect that the current leaks are an internal issue of the PSoC processor. What could cause this type of leaks? What precautions can be taken to prevent this leaks? And why is the leak current so variable?


      Thanks in advance for your help,