2 Replies Latest reply on Sep 14, 2017 11:01 AM by user_148813134

    Current consumption too high in sleep mode after migration to another device

    user_148813134

      We migrated our design from a PSoC Cy8C3246 to a Cy8C3466 and moved some pins in the PCB in order to optimize our hardware design for the analog parts. Now we see that the total current consumption during sleep () is elevated from 8µA in the original design to a variable range from 200µA to 1200µA.  In order to be able to pinpoint the source of this current, we've built a dummy project configuring all pins in the proper mode and level acoording to the hardware design. We use a sleep mode with a 1PPS wakeup timer. The proper functioning of the sleep function is monitored using the uart_putchar() function. All hardware pins have been measured with an oscilloscope  in order to detect unaccounted signal levels . Internally no devices other than the uart  for debugging purposes and all hardware pins are defined in the TopDesign level. Even removing some components from the PCB did not solve the problem. Furthermore, the problem is found in all tested devices of our production batch. We suspect that the current leaks are an internal issue of the PSoC processor. What could cause this type of leaks? What precautions can be taken to prevent this leaks? And why is the leak current so variable?

       

      Thanks in advance for your help,

      Kris

        • 1. Re: Current consumption too high in sleep mode after migration to another device
          anks

          Can you please share your project with us

          • 2. Re: Current consumption too high in sleep mode after migration to another device
            user_148813134

            The problem seems to be the usage of pin P15[0] and P15[1], in our case defined as resp. sclk en miso pins to an SPI interface. The mere fact that these pins are defined as such in the TopDesign / cydwr (even with external components removed from the PCB) causes these current leaks during sleep. Trying to alter the drive mode of these pins to 'high impedant analog' before entering sleep mode does not change this behaviour. Any suggestions anyone to solve this issue without a hardware redesign?

             

            In attachment you'll find the project in which we simulated the problem. There is a pin named P15_0. When this pin is mapped to any free pin except P15[0] or P15[1] the current consumption in sleep is as expected. (ca. 6..8 µA). When rebuilding the project with this pin mapped on either P15[0] or P15[1], in any configuration (analog high impedant, digital input, digital output,...) the current consumption in sleep is above 100µA. Note the we removed all hardware components from our PCB in order to avoid leaks through these components.