5 Replies Latest reply on Aug 23, 2017 4:52 PM by user_15770712

    Synchronization of DMAs


      Hello everyone, I am looking for your help in solving the following case:


      I need to sample in parallel two sine signals.


      For this, I have two ADCs (SAR) in PSoC5LP working at 1 Msps, as shown in the figure below. Each of the bypass capacitors have been connected to the PSoC5 pins and the configure system clock meets the requirements for the mentioned sampling frequency.


      Clock System Configuration.jpg


      Each "eoc" output of these ADCs is connected to a separate DMA channel which stores the respective ADC data (ch1 and ch2).

      Activation of the DMA channels and the start of conversion of the ADCs are carried out with the firmware using the following APIs:


           CyDmaChEnable(DMA_Ch1_Chan, 1);

           CyDmaChEnable(DMA_Ch2_Chan, 1);




      Then, if I use the same input sine signal for the two ADCs (Pin_Ch1 and Pin_Ch2) and assuming that the acquisition happens in parallel, the graphs of the results should overlap.

      However, it is obvious that there is a delay, but I have not managed to be "constant" and therefore the results are random. That is, sometimes the results overlap and in other cases the data have delays.


      So how can I achieve my parallel acquisition requirement or with a constant delay?

      What are your tips?