We are glad that you already have completed a design with PSoC 6. I am hoping all is going well with the bring up and the testing.
As you correctly noted, PSoC devices are designed to increase integration and reduce external BoM. Note that PSoC 6 (as compared to PSoC 3 and 5) has multiple power rails and power input pins. This does not necessarily translate into a high number of external components. Have you been able to take a look at our Hardware Design Guidelines for PSoC 6 here: PSoC 6 BLE Hardware Design Considerations_Full_Draft ?
The CY8CKIT-062-BLE kit implements all recommended parameter values and layout techniques to get the best possible performance from the device. In the kit, we recommend using a 2.2 uH, 1.2 A, and 0806 (2 mm x 1.6 mm) package. Are you using a similar inductor? Also, as you mentioned, you could use the resonance free/polymer capacitors; but please note that this might have a cost implication as well.
If you could share your schematic, and also your system requirements, we could help optimize your design. If you are not comfortable sharing the schematic on a public forum, please do send me an email or create a technical support case and ask it to be routed to PSoC 6 applications.
We will definitely consider your feedback in improving the hardware design guidelines application note.
Thanks for your feedback.
Yes, I followed the Hardware Design Guidelines for PSoC 6 as stated in the pdf and also took reference of the CY8CKIT-062-BLE kit as well as the recommended Murata coil.
I'm able to share my design, I'll mail it to you directly.