Just to help things along, here is the actual error message I get:
ADD: sdb.M0059: error: Error in component: ADC. Internal clock frequency value must be between 1 MHz + 1% (1.01 MHz) and 18 MHz - 1% (17.82 MHz).
You might want to increase the BUS clock of PSoC5 LP Devices.
This looks like a bug to me. The calculation of the allowed frequencies seems to get the boundaries wrong - it should be "1MHz-1% up to 18MHz+1%". The way the error is displayed means one cannot get the full sample rate, since the component would not accept a 18MHz clock.
I also tested it with an external clock - same problem. Lowering the frequency makes the error go away.
What clock frequency did you use to get it to work?
Anything less than 18MHz did work (I tested with 12 and 16MHz), but then you don't get the full sample rate. (But beware - I tested only the compile, I don't own a PSoC5LP board yet).
The original PSoC 5 products could not run at the full 1M SAR ADC sample rate.
The new PSoC 5LP parts are full pin-for-pin replacements and are capable of running at the full 1M sample rate.
Creator knows via part#, which family of PSoC 5 you have, and will limit your sample rate.
The -050A kit contains the old silicon. The latest kit is a -050B and it contains the production ready 5LP silicon.
The upgrade site is below:
Try putting this part# into creator: CY8C5868AXI-LP035
Hope this helps...
Actually the problem we are discussing here is that even for the 5LP, one cannot use the full sample speed. If you feed a SAR ADC component with a 18MHz clock, PSoC Creator gives an error about the clock frequency.
I am now running PSoC Creator 2.2 SP 1. I am still having this issue. Is there any knowledge base article or resolved method to get the full 1 MSPS without a build error?
This the cause of the problem(PW of clk) -
This text box is a read-only (always grayed out) area that displays the required clock rate for the
selected operating conditions: resolution and conversion rate. It is updated when either or both of
these conditions change. Clock frequency can be anywhere between 1 MHz and 14 MHz
(18 MHz in PSoC 5LP). The duty cycle should be 50 percent. The minimum pulse width should
be greater than 33 ns (25.5 ns in PSoC 5LP). PSoC Creator will generate an error during the
build process if the clock does not fall within these limits. In that case, change the Master Clock
in the Design-Wide Resources Clock Editor.
18 Mhz = 55.5 ns, so perfectly square clock will not work. If square in 5LP then clk = 51 nS =
19.6 Mhz. But error takes into account tolerance, looks like limit is 17.82 Mhz max.
Error in component: ADC_SAR_1. Internal clock frequency value must be between 1 MHz + 1% (1.01 MHz) and 18 MHz - 1% (17.82 MHz).
I tired config with a xtal and got close to 18 Mhz, error for that was -
Error in component: ADC_SAR_1. Internal clock frequency value must be between 1 MHz + 0.001% (1.00001 MHz) and 18 MHz - 0.001% (17.99982 MHz).
I used 0% error for xtal config, but looks like tool defaults to .001 % as minimum tolerance,
in case of xtal. Maybe try external digital 0% error clock and see if that allows 18.000000 Mhz.
A bit of an exercise.
No, this won't work either. Error message is the same. To me the SAR ADC is broken in that regard (and the sequencing SAR ADC too), one cannot use it with maximum sample rate.
Though one could import the component and change the validation (the check is in cyadcsarcontrol.cs)
While you are at it, you can file a bug against the static timing analyzer as well for not figuring out the real clock to the ADC :)
But well done, this is a clever idea!
Case filed, I will update this when results are in.