Hi ftoffolon, I/O pin and interruption these have many setting points. Input mode, Transparency, Buffer mode or Selection of edge...etc. You rather upload your project as bundle that is good. When you do that you can get more helpful advices.
The input clock has extrmely slow rise/fall times, read input spends excessive
time at threshold region of input buffer = potential to oscillate. And that would
be aggravated by noise on top of input being at threshold. That could account
for your seeing a much higher Timer OV, eg it would be clocked at a rate >>
1) How did you signal condition line Vin to pin ?
2) Consider using a comparator with Hysteresis as conditioning for Vinac.
If you only need the AC signal for clock input source, you don't need zero crossing, Just use a compartor with hysteris to get a 50hz pulse, set the compare level away from 0V. you will not get 50% duty cycle, but as a clock source, it doesn't matter.
50Hz is relatively slow. It's a LANT signal that has slow rising and slow falling.
Therefore, Signal conditioning is important. as dana say.
Let me show you one example of external circuit.
Other precautions is voltage at input pin needs to clamping.
If this value excess Vdd and Vss, psoc is going to restart or break down.
Thanks all for quick replys,
actually I simulate mains freq. using a function generator that drives a square waveform (0 - 5Vdc, 50Hz), so now I don't mind over/under voltage consideration (now I'm still work with pioneer kit).
As suggest into psocsensei forum (thanks Bob 4 link), I've tried to route the clock generated through zero cross input as direct as possible to another output pin for check freq and it's good, but still problems on count. It's seem timer (fixed function one, because my target is cy8c41xx, so without UDB) runs with another clock, with ~50*5kHz freq.
Pin that reads zero cross signal is configured as dig. input with hi imped., input buff. enabled and trasparent mode for synch (others kind of sync. has no effect).
Extract from an example schema from another product with uC (PIC16/18) with internal clamp diodes, that I can plan to use
for zero cross signal conditioning :
*230 Vac - 50Hz into R3
*zero cross to PSoC, eventually with external clamp diodes (if there're no internals or there're current problems, I'll check datasheet better).
In that example there's no hyst. comp because the realted uC that use it has schmitt trig. for each I/O. I'll plan to check if hyst. comp. is required for this clock input.
Max pin injection current is -
You are using a function generater for the input signal.
But didn't work.
I doubt to comparator of PSoC4,
that is FF module not UDB module that has no intenal reference voltage.
And also PSoC4 seems has no analog reference module.
Therefore, you owe to give it by external reference voltage via analog pin.
It might be 1V to 2.5V is well.
Add this to negative input of comparator.
Input clamp circuit is still need.
Take look this result.
Thanks dana & PSoC73,
you're right about use external clamp diodes for limit injection current for PSoC4 applications.
I've done more test : always with clock generated by ext. pin (50Hz from ext. freq. gen., a square wave, 5-0Vdc) that drives FF timercounter that I want to use for 1 second period tick isr, if I disconnect ext. clock from pin, timer still runs and generate ovr isr, always with a ov interrupt period with a freq ~ 5kHz.
Other test : if I drive timercounter with 50Hz derived by HFCLK (I'ev checked it into clocks tab of cydwr file), it works good and generare interrupt every seconds. Instead if I get this 50Hz internally generated and put into a toggle flip flop (e.g.) and route the filp flop Q out to a new design-wide clock and route this new one to the timercounter, same behavior than I/O driven clock.
It seems to me that clocks built from design-wide isn't good for fix funct. timercounter. From timercounter datasheet I've read this into Clock Selection paragraph:
"The clock is provided using the clock terminal. This clock must be from the global clock
generation logic. Clock prescaler functionality is available within the TCPWM component. "
Does "global clock generation logic" means clock that cames only from internal clocks (through divider) ?
Not my place to ask, but consider filing a tech case at -
“Create a Case”
and let forum know result.
Just give them the link to this thread as basis of CASE.
From TRM on Reference -
The PSoC 4200 reference system generates all internally
required references. A 1% voltage reference spec is provided for
the 12-bit ADC. To allow better signal to noise ratios (SNR) and
better absolute accuracy, it is possible to bypass the internal
reference using a GPIO pin or to use an external reference for
Note reference can be accessed external by choosing external bypass on A/D
and using that pin. It would be unbuffered however, beware of loading.
Reference not necessary for Comparator in this problem as goal is not absolute
trip voltage, rather implmenting Hysterisis to help eliminate noise from 50 Hz
input. And take care of too slow a rise/fall time forcing input buffer to sit in its
active region too long.
I've created a tech case and I'll keep the forum in touch for any news. Thanks to all. fabio
"I doubt to comparator of PSoC4, that is FF module not UDB module that has no intenal reference "
The comparator is not a FF module. It is an analog comparator with selectable Hysteresis.
The comparator reference is either its Inv or NonInv input.
Hi everybody, after tech case creation and some info exchange between cypress support, the result (and so the close) of my ticket is that in PSoC4 is not possible to use external clock as the clock source for TCPWM block while using IMO as the source for the other blocks, as mentioned on PSoC4 TRM's page 61. Tech support said to me that this restriction isn't present on PSoC3 and PSoC5. I've suggest to enhance PSoC Creator to report this when trying to use different clock source, because now nothing is shown, only strange behaviors on project that starts the developer's witch hunt. Regards, Fabio.