9 Replies Latest reply on Jan 14, 2016 10:29 PM by user_246598725

    Port 3.x not usable as output if CapSense enabled?

    user_246598725

      Hi,

         

       

         

      I'm struggling into the next pitfall while 'exploring' PSoC 4 ;)

         

      I'm using a Pioneer kit and want to output a signal on port 3.6. The CapSense part (5-pole slider on port 1.1-1.5) is also enabled, which means that P4.2 is used as Cmod.

         

      Now, PSoC Creator tells me that port 3.6 cannot be used when P4.2 is configured as Cmod (error: pl.M0046:E2725 P3[6] cannot be used as an output when P4[2] is used as Cmod).

         

      Great...

         

      I've gone through datasheet and reference manual, but I couldn't locate anything indicating that port 3 has reduced capabilities if CapSense is enabled.

         

      So, I'm getting a bit frustrated because I've to fight with UDB & Verilog and maybe incomplete datasheets/reference manuals or a faulty implementation in PSoC Creator - but where's the error?

         

      I connected Cmod to P4.1 to 'test' it (P4.2 is fixed function for Cmod) - interestingly, in this case Creator only throws a warning that automatic rerouting has been done, but it compiles successful.

         

       

         

      Regards,

         

       

         

      Ralf

        • 1. Re: Port 3.x not usable as output if CapSense enabled?
          user_1377889

          You are he world of PSoC4 which has a lot of restrictions to support a low-budget chip. Without knowing your concrete project I would guess an internal routing problem to be the source of your error / warning. When Creator has to route a signal to a specified pin it may use a different pin and then "hop" by placing a route between them to the endpoint-pin.

             

          Solution / Workaround: Let Creator decide which pin to use, so do not assign (at first) a pin to the signal.

             

           

             

          Bob

          • 2. Re: Port 3.x not usable as output if CapSense enabled?
            user_246598725

            Hi Bob,

               

             

               

            I can accept that a low-budget chip will have some restrictions, but those restrictions should also be mentioned in the datasheet and/or reference manual.

               

            I tried your suggested approach, it compiles with no errors if Creator can choose the pin assignment at his own. Then I assigned the pins manually step by step. It seems that at least P3.6 is affected if CapSense is active.

               

            Again, this can be accepted for a low-budget chip if it is mentioned in the relevant documentation.

               

            I think the next step is to open a support case for clarification by Cypress.

               

             

               

            Regards,

               

             

               

            Ralf

            • 3. Re: Port 3.x not usable as output if CapSense enabled?
              user_1377889

              Have a look into the PSoC4 Architecture TRM.

                 

              On page 196 fig. 19-3 you find a picture that shows the internal pin connection capabilities and restrictions. No need to file a technical case, it's all there.

                 

               

                 

              Your problem might result from choosing a PSoC4 as your first PSoC. Many other users have (due to historical facts ) choosen a PSoC3 (poor CPU core) or a PSoC5 (now LP, good choice!) which both seem to have no restrictions in routing or even the amount of resources. Of course there are, but it may take some time until you hit that wall.

                 

              On the other side, the PSoC4 is targeted for just $1 while the price for a PSoC5LP is quite a bit more!. Additionally the Pioneer board offers a commonly used interface which reserves some of the few pins for dedicated functions.

                 

               

                 

              At the price of 4 Pioneer boards you can get a PSoC5LP Development Kit which is VERY versatile and comes with (nearly) no restrictions in routing. On the other hand you will have to jumper / wire all connections yourself making it difficult to explore different projects at the same time without re-wiring all your external connections.

                 

               

                 

              Do not throw the helve after the hatchet! (need a translation for that idom )

                 

              Bob

              • 4. Re: Port 3.x not usable as output if CapSense enabled?
                user_14586677

                Comparison of PSOC 3/5LP fairly straightforward as primary difference is

                   

                core. Remaining resources fairly well matched, table of attributes here -

                   

                 

                   

                    

                   

                          http://www.cypress.com/?rID=2545

                   

                 

                   

                But comparing PSOC 4 a little more involved as its fixed resources

                   

                substantially different than 3/5LP. As well, often overlooked, is

                   

                a single cycle 32 bit multiplier.

                   

                 

                   

                Like trying to compare a Tractor and a Scooter, they really are targeted towards

                   

                different markets/designs/problems.

                   

                 

                   

                Not to mention unit price of PSOC 4 ranges 1/12 to 1/5 that of PSOC 3/5LP.

                   

                 

                   

                Regards, Dana.

                • 5. Re: Port 3.x not usable as output if CapSense enabled?
                  user_246598725

                  Hi,

                     

                   

                     

                  @Bob:

                     

                  Thank you, but I couldn't figure out why the mentioned figure 19.3 is relevant for my problem. The figure describes some analog routing, and I want to output a digital signal. Also the figure doesn't show why P3.6 might be affected when using P4.2 as Cmod. Also it's still confusing why assigning Cmod to e.g. P4.1 will result in a successful compile. That's why I assume it's a bug.

                     

                   

                     

                  @Dana:
                  Right, they're targetting different markets. That's why I wrote I can accept restrictions, but then they should be mentioned clearly in the TRM or datasheet
                   

                     

                  Regards,

                     

                   

                     

                  Ralf

                  • 6. Re: Port 3.x not usable as output if CapSense enabled?
                    user_78878863

                    I think you should file a support case (under Login / MyCases) - it might be you found a bug. I etsted with just a simple project (just one control register with a digitial output pin and a CapSense block in standard configuration). I was able to assign the output to P3[0], P3[4] or P3[5], but not P3[6]. And I cannot se any reason for that - from routing perspective they are all the same.

                    • 7. Re: Port 3.x not usable as output if CapSense enabled?
                      user_246598725

                      Hi hli,

                         

                       

                         

                      yes, I already opened a support case, waiting for feedback.

                         

                       

                         

                      Regards,

                         

                       

                         

                      Ralf

                      • 8. Re: Port 3.x not usable as output if CapSense enabled?
                        user_246598725

                        Status update:
                        Cypress confirmed that P3.6/P3.7 can't be used as output if Cmod/Cshield are enabled on P4.2/P4.3. This is expected behaviour and will be mentioned in an application note released in the near future.

                           

                        IMHO such things MUST be shown in the datasheet/reference manual and not in an application note being released sometime after chip release.

                           

                        It's still not clear why Creator accepts the design if Cmod is connected to a pin other than P4.2, but it seems this behaviour will not be considered as a bug by Cypress.
                         

                           

                        Regards,

                           

                         

                           

                        Ralf

                        • 9. Re: Port 3.x not usable as output if CapSense enabled?
                          tica

                          If anyone is looking for that app note, it's here:

                             

                          http://www.cypress.com/file/141176/download

                          • 10. Re: Port 3.x not usable as output if CapSense enabled?
                            user_246598725

                            Hi Tim,

                               

                             

                               

                            thank you for updating the topic. If I remember correctly, the app note was not yet ready at the time I faced this problem.

                               

                             

                               

                            Regards,

                               

                             

                               

                            Ralf