These might help -
I looked at them before I posted - great information but they all seem to use significant resources. The best way I found to date is this little I2C controller from NXP: http://www.nxp.com/products/interface_and_connectivity/i2c/i2c_bus_controller_and_bridge_ics/PCA9629APW.html#support
But always worth asking if there is a crazy cool way of doing it on a PSoC that I missed. . .
If the concern is stepping the motor without software lag making jerky motion, you might want to considder using the UDBs to build the interface so that it will operate along side of the processor code. According to the A3967 datasheet, you are required to have a step frame of at least 2 uS, with 1 uS on and 1 uS off on the step pin, so this looks like a job for a timer/PWM/ or just a Datapath state machine. So, esssentially, the PSoC isn't generating the phasing of the motor, the controller is, and the only thing the PSoC need do is generate a pulse at a consistant rate, which is not that far off from the brushed DC motor with which you have been working.
smooth acceleration of the motor can be achieved by using smart use of the micro-stepping pins, MS1/MS2 to select between full,half, etc. and that can be based on the distance you need the motor to travel, or ramped up when starting/stopping the motor. on the A3967, there are 4 step sizes that can be achieved, which can be used to move to a precicse position, or used to control the speed of rotation with a constant step pulse stream being generated from the PSoC.
Hope that helps!
A3967-Datasheet.pdf 435.1 K
Yes, it seems that combining the step sizes can give some cool features.
Generating the pulses will all have to be done in hardware. Or using a serial sender ( UART TX ) and a buffer - just preload the set word in the buffer based on how many steps I need to take ? than set the Bits per sec as speed - this limits the speeds to discrete BPS vals but it should work without CPU - I think ?
At this price maybe buy another PSOC 5LP and add a bare fet driver.
You cannot copy the inside of that device because there is a significant
amount of slew, thermal, regulation, and other analog stuff. You could,
with some effort, implement partial synthesis of the functionality of the
analog with PSOC + external sensors, components. But messy.
You can of course copy some of the digital into PSOC.
Most cost effective approach is external power driver with or without MOSFETs,
at minimum gate drive capability, with thermal, and PSOC for control.
Thanks for all the info! I thought it's a nice option to also get a PSoC and emulate the I2C driver - that has loads of distributed computational potential.
For the moment I ordered a pair of these ICs: PCA9629A - hopefully they will work well but I'll let you know as I test.
Becuse of motor driving currents and transients layout and bypassing is
everything in the design. Hopefully these will help -
http://www.cypress.com/?rID=39677 AN57821 - PSoC® 3, PSoC 4, and PSoC 5LP Mixed Signal Circuit Board Layout Considerations
http://www.cypress.com/?rID=40247 AN58827 - PSoC® 3 and PSoC 5LP Internal Analog Routing Considerations
http://www.cypress.com/?rID=39974 AN58304 - PSoC® 3 and PSoC 5LP – Pin Selection for Analog Designs
So... just to post some updates. The I2C driver seems to be ok, however it needs an extra high current IC, increasing complexity and cost.
I have found this little guy: https://www.sparkfun.com/products/retired/13226 ( based on the Allegro 3967 IC ) which only needs a pulse train and a direction pin.
My big question now is .... How do you think would be best to generate a specific length pulse train from the PSoC ? I need to generate X pulses and know how many I have output and also do other things in the mean time - I don't want to block the CPU.
I am thinking of a timer that will give me the pulses at a specific frequency. However I need a counter with that to know how many pulses I have generated.
Or maybe a down counter that would count the pulses than stop on zero.
Any ideas are welcome :) - Thank you!
The interrupt system of the PSoC5 is fast enough to handle a timer counted down to zero. More challenging will be to vary the pulse frequency to allow for start ramps having the stepper running at faster speeds.
Given that you want a pulse train counted w/o CPU intervention, a Timer or PWM
to develop the pulses and a counter that counts the pulses and gates N pulses for
you. Fairly simple, down counter could gate the timer enable off with a D and you
use a control reg to reset the D to initiate another burst of pulses. Or basic variants
of this scheme.
So... I tried to do the checks and stops in software with no luck. The biggest problem I have is to capture accurately when the pulses are done, i.e. count complete and be able to restart after. I didn't find any good way to store the TC/ Comp pulse and use that.
The hardware solution you mentioned Dana seems better. But trying a SR Flip Flop led me nowhere - I can't set it up so it stops after steps are done and waits for a reset from register.
I am thinking I could disable PWMs once steps are done or set the pulse to zero. Than, for a new command reset counter and brings pulses back to desired speed. The scenario is:
I set it to do X steps. Once it finished it will stop. Than I either run again, keep speed zero or set a new step number.
Regarding speed setup, it's very easy, just change the PWM frequency and it sends more pulses - hence higher speed.
This should in theory be a simple problem- capture pulse from TC/Compare in a SR and that sets my PWM to zero. Also updated a value in a sticky status register. Than I read the reg and if pulses are done update new command.
No idea why it will not work.