8 Replies Latest reply on Jul 6, 2015 5:26 AM by user_14586677

    Warning - hold time violation found in a path from clock

    masterpupsik

       Hi,

         

      I'm trying to build my project, but I get the following error which I can't seem to solve:

         

      sta.M0019:  hold time violation found in a path from clock (cyBUS_clk) to clock (Pin_5(0)_ SYNC/OUT)

         

      My project includes 1 SPI master and another (not related) SPI slave blocks.

         

      I suspect the problem is due to the SPI slave which is controlled by an outside clock.

         

      I've attached my project top design schematics.

         

       

         

      Thanks in advance,

         

      Igal Nudelman

        • 1. Re: Warning - hold time violation found in a path from clock
          user_1377889

          Welcome in the forum, Igal.

             

          Your SPIS component's MOSI-pin (Pin_4) uses double sync at its input that is causing the warning. When set to none (no syncing) the warning passes.

             

           

             

          Additionally: I would suggest to use an internal clock, since there is no need in your case for an external one on Pin_33. This clock is not controlling the bit-rate, it is for the component's internal updating of the states.

             

           

             

          Bob

          • 2. Re: Warning - hold time violation found in a path from clock
            masterpupsik

             Thank you for your quick reply Bob.

               

             

               

            Could you please tell me how to disable the syncing option of Pin 4? I didn't find it.

               

             

               

            Best regards,

               

            Igal

            • 3. Re: Warning - hold time violation found in a path from clock
              user_1377889

              Configure the pin as attached picture

                 

               

                 

              Bob

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              • 4. Re: Warning - hold time violation found in a path from clock
                masterpupsik

                 It worked!

                   

                 

                   

                Thanks a lot for the answers and the warm welcome 

                • 5. Re: Warning - hold time violation found in a path from clock
                  user_1377889

                  Fine that I could help you. You are always welcome.

                     

                   

                     

                  Bob

                  • 6. Re: Warning - hold time violation found in a path from clock
                    user_14586677

                    Some thoughts -

                       

                     

                       

                    1) You do not have hysterisis enabled on the comparators, if your

                       

                    compare signal is noisy you might want to consider that.

                       

                     

                       

                    2) You used up all your comparator blocks, if you needed more consider

                       

                    using the scanning comparator block, and if the references need to be channel

                       

                    specific use a mux for that as well. Or use the SAR, its capable of 1 MSPS, and I

                       

                    noticed your comparators set for slow speed, eg. 200 nS response time. It also

                       

                    gives you much more control over equivalent reference trip points.

                       

                     

                       

                     

                       

                     

                       

                    3) You used IDAC followed by TIA, I assume to get a VDAC ? You can always terminate

                       

                    the IDAC with an R to get a VDAC. Disadvantage is its not buffered, however if its destination

                       

                    is hi Z then would work. Even if it was R based load of known value you could use that R in

                       

                    the determination of IDAC R.

                       

                     

                       

                    4) The IDAC uses a ref of Vdd /2, so you limit your range to Vdd / 2, is that what you wanted,

                       

                    or would just Vdda as a ref, which increases range, be more useful.

                       

                     

                       

                    Regards, Dana.

                    • 7. Re: Warning - hold time violation found in a path from clock
                      masterpupsik

                       Hello Dana,

                         

                      Thank you for your suggestions.

                         

                      1. I might add hystersis, not sure about it at the moment.

                         

                      2. I know I used all my comperators, and it doesn't look like I'll need more. I don't think I can use your suggestion for scanning comperator block because I need different values (and the ability to control them) to be compared to.

                         

                      In addition to that, I need this process to be fast (<6uS) and the SAR won't give me this speed (it's 1MSPS for 1 bit).

                         

                      3. You're correct. I used IDAC to get VDAC. When I use Vdd/2 reference and I change the current direction (sink or source) I can get 9bit VDAC for 5V instead of the VDAC that PSOC offers that's set to limit of only 4V and 8bit.

                         

                      The TIA is for buffering and some filtering as well.

                         

                       

                         

                      I hope my answers will give you new ideas for your future projects.

                         

                      Best regards,

                         

                      Igal

                      • 8. Re: Warning - hold time violation found in a path from clock
                        user_14586677

                        2. I know I used all my comperators, and it doesn't look like I'll need more. I don't think I can use your suggestion for scanning comperator block because I need different values (and the ability to control them) to be compared to.

                           

                         

                           

                        Thats code, you have infinite flexibility for comparisons to a reference V of your

                           

                        choosing, to the A/D value measured. You can even make it adpative.

                           

                         

                           

                        In addition to that, I need this process to be fast (<6uS) and the SAR won't give me this speed (it's 1MSPS for 1 bit).

                           

                         

                           

                        SAR yields a 12 bit conversion in 1 uS. However to your point you do the conversion

                           

                        and then execute some code, not much I would add. If you use SAR at 10 bits it

                           

                        will do 1.125 MSPS, at 8 bits even faster, 1.285 MSPS.

                           

                         

                           

                        The suggestions are simply in case you run out of HW resources.

                           

                         

                           

                        Regards, Dana.