Please let me know if you have a chance to try it out.
Just wondering if anyone outside of Cypress has used this flow.
Can you update this with a procedure for simulating with open source tools (ie. Icarus + jVerilog or some other tools)?
I'm not a student so I can't use the student edition and the purchse price of the (non-vendor specific) ModelSim PE appears to be very high.
Is ther any proteus simulation library file for PSoC C8CKIT-049-42xx.
if there it is, post the link.
Good stuff. I am in the process of setting up a test bench for my project.
Is this the most recent version of the model? I noticed that the clo chaining signal seems gotten reversed for the disabled state (4'b1111 -> 4'b1101 at lines 548/550).
Incidentally are there any tips for settling down undefined states? I've got a couple of spots where I don't particularly care about an initial 0/1, yet in simulation the 'X's tend to propagate back through the control path. Or perhaps that should serve as a warning sign to a HDL newbie to take care with resets, even at the cost of additional gates.
Poking about a bit further I believe shift-right output on line 685 should be alu_out and not s_r_input. Otherwise the post-shift LSB is gets carried out instead of the input one.
The fifo_blk_extra/block reset to 0 at line 753 in input mode seem incorrect, where they would induce a phantom read. At least the I was unable to induce a glitch by clearing the FIFO via ACTL, which the TRM documents as being interlocked with the reset. The bulk of the output registers, along with the aforementioned FIFO clear, also seem to have been omitted from the reset circuit.
I apologize for nitpicking and realize this isn't exactly an officially supported product but the precise semantics of the datapaths are quite difficult for me to grasp and reason about, and so an accurate simulation model would be an invaluable aid in development.