9 Replies Latest reply on Jun 30, 2015 8:48 AM by user_515762956

    verilog and datapaths

              Hi. I'm looking for examples of using Verilog and expose/consume data that is shared with the CPU. All examples showing verilog and datapath's seem to skip that part. I'm trying to write a component that receives a 24-bit pulse train and exposes it to the CPU for use with a PID controller. Initially, I thought I would clock these values into a verilog reg and then latch them to a register that I could read from the CPU. It also appears that I could skip the entire part and shift them into a datapath and read it from the CPU. But, no examples of anything like this exists (reading verilog values from the CPU). Also, I need to output 5 configuration lines. I thought a control register would do it, so I mapped 5 lines of the control register to the outputs (on my symbol definition). When I build the API side, I always get a "_REMOVED = 1u" for my symbol. FYI: The component I trying to use is TI's ADS1274 - a 24-bit ADC with 4 simulatenous outputs. Any advice, or any good place to get info about DataPaths that aren't already in the documentation (yeah, I already read the manuals provided).   
        • 1. Re: verilog and datapaths

          Welcome in the forum!


          There are different ways to access an UDB-component


          There are a parellel-in and -out bus for signals into the UDB which migt be connected to a control register


          There are two FIFOs with the appropiate signals which you may read or write data from/to.using the CPU*


          You may even use DMA (on a PSoC4-M) to get data in/out the FIFOs


          You may write data directly into the D-registers and read from them


          Keep in ming that an UDB contains some (not few!!) PLD logic that allows to create counters shifters digital comparators etc without using the ALU


          There are some "Cheat Sheets" (type that into the keyword search on top of this page) helping you to create a working 24-bit wide component.




          *It is not magic: If you know the name of an item, you can control it! Since the position of a component may vary from built to built there are some names generated in the component's .h-file to access the internal registers. A self-written component has to provide this .h-file as well and now it is your responsibility to create the appropiate #defines for accessing the internals. In the "Component Author Guide" chapter 6.4 are those secret names listed. Use those with wisdom and care





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          • 2. Re: verilog and datapaths

            Keep in mind that there is a rather powerfull hardware-optimizing step. All unused hardware will get optimized out. So a component which's outputs are dangeling and are not connected to a pin will vanish into thin air!





            • 3. Re: verilog and datapaths

              Have you seen Brad Buddings blog, I think he addresses a number of datapath


              issues, like parallel access -








              Regards, Dana.

              • 4. Re: verilog and datapaths
                        Wow, a whole bunch of replies overnight..... After playing with the Sparkfun board and seeing with PSoC5 and Creator can do, I got a few of those USB kits, you know, the $10 ones. I convinced my boss to use this in a production design, now I just have to figure out how. :) We are upgrading from a PIC18, because of configurable pins, and industry standard GCC compiler, as opposed to fixed pins and and propriety compiler. Bob Marlowe - I think because I didn't generate an API hook for my control reg, it get dumped. I'm familar with Verilog dumping things, but not, generally outputs. Going to really digest WaveCapture, as it uses DMA, IRQ's, etc. I downloaded a community component and in the process of dissecting it. (WaveCapture). A good paradigm - connecting a status to a control reg. danaaknight - going to check out the blogs later. Thanks guys and gals(?) -- Ken   
                • 5. Re: verilog and datapaths
                          sorry for the bad formatting. I only get a two line - 1 inch area to post a reply - probably a browser issue.   
                  • 6. Re: verilog and datapaths

                    When using ms ie as browser switch on "compatibility mode".





                    • 7. Re: verilog and datapaths

                      ...by the way: Has BlackTiger anything to do with PinkPanther?





                      • 8. Re: verilog and datapaths

                        In the keyword search field on the forum page type in "brad budlong datapath",


                        quite a few hits.




                        Regards, Dana.

                        • 9. Re: verilog and datapaths



                          The Brad blog stuff (PSoCSensei) is the absolute best.  After watching several times because the info is so dense, I am now dangerous because I believe I know what I'm doing.


                          THEN ---- a moment of reflection.  Why was I using Verilog?  I still needed to make stuff glitch-free, implement interrupts handle the FIFO and DMA....  In the 15 minutes it took me to have my morning coffee, I did it using the regular schematic.  A 24-bit shifter, and counter and an edge detect --- and I was basically done and had all the features I would still have to implement in Verilog.


                          Now I just feel silly.  It was just too ingrained in me -- can't use SPI Master, so I must use Verilog. 


                          Also, I noticed that the entire library is there, loadable and modifiable, if needed.  The PSoC Creator and Cypress has just overtaken Altera for the best development tools (Microchip, Atmel and Xilinx don't even deserved to be mentioned). 


                          And best community forum support EVER.


                          Now, we just need a good hardware simulator, as I'm still stuck with Icarus Verilog.


                          Thanks again folks,