1 2 3 Previous Next 42 Replies Latest reply on Oct 21, 2013 4:57 PM by kaonc_282686

    How to make DDS module

      Hello PSoCers     



      I am willing to submit this article.     



      Still getting started this component division.     



      i am afraid of some rudeness of mine.     



      don't know the rule of this division yet.     






      In my practice, DDS module become working.     



      There are many items to have improvements.     



      I want to listen to how to get more efficiency.     



      Want to listen to critique from everyone     






      I have been work with Xilinx CPLDs,     



      those works are mainly schematic-base design.     



      I am new to PSOC CPLD and Warp-Verilog.     






      Keep it up rolling !     


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