6 Replies Latest reply on Mar 23, 2015 10:31 AM by userc_41638

    IP for FPGA to configure sync slave fifo


      Hello I am workin on the project about the creation of Ip in vhdl to communicate avec FX3 in sync slavefifo mode.


      are there any people that have already work in this part of subject to give me some advices about that or anything that can help me ?


      my goal is to establish communication between FPGA(Ip) ====>FX3 (just one signle side). To do that  I must use timing from sync slave fifo but this timing seems not really easy to understand.