11 Replies Latest reply on May 11, 2015 11:44 PM by james.fry

    PSoC 5 clock questions

    user_463759797

         I see there are several clock sources for the PSoC 5.  They are plainly described.

         

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        However, I do have a few questions concerning the information I read:

         

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      1)  The PSoC designer assumes 24 mhz.  Are there any design tradeoffs if you use an 18 mhz clock as the input?  (I'm assuming you can't use USB if you do that.)

         

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      2)  If I wish to use a base 18mhz clock off of the IMO oscillator, can I do it? There does not appear to be a way.

         

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      3) Are there any example projects using the DSI (dsi_clkin) as a master clock?

         

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      4) Can you drive the Pierce Oscillator input (AN54439) using an external Clock Oscillator device?  Any tradeoffs?

         

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      5) If I must use a 24mhz input clock (say, for USB), how would I get an 18mhz stable clock for the SAR ADC to do 1msps?

        • 1. Re: PSoC 5 clock questions
          user_1377889

          There are different clock sources as you have seen already. Central clock is the IMO which can be fed internally, external x-tal or external clock. From the IMO the other clocks are derivated by use of a PLL and some dividers.

             

          1)  The PSoC designer assumes 24 MHz.  Are there any design tradeoffs if you use an 18 mhz clock as the input?

             

          You do not need to, but you may. You can set the PLL output to 36MHz from a 24MHz IMO, and set the master clock and/or the bus clock to something like 36,18 as you like.

             

          2)  If I wish to use a base 18mhz clock off of the IMO oscillator, can I do it? There does not appear to be a way.

             

          No, there is no way except with X-tal or external clock. I usually use 3 or 24MHz

             

          5) If I must use a 24mhz input clock (say, for USB), how would I get an 18mhz stable clock for the SAR ADC to do 1msps?

             

          Running the SAR ADC at 1Msps requires the use of an external clock or an X-tal preferrably at 24MHz. From that you can derive the 48MHz clock for USB, the 36MHz coming out the PLL from which you can derive a clock-component on the schematic with 18MHz. The bus-clock and themaster clock are both derived from the PLL directly.

             

           

             

          Bob

          • 2. Re: PSoC 5 clock questions
            user_463759797

              I played around with a non-standard clock (34mhz), and the "hall monitor" gave me red for USB.

               

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            Until I was able to either give it a 48mhz clock on the USB, or turn it off altogether,  the system errored and would not build.  I was able to get a build by unchecking the USB clock box in the GUI. 

               

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            Are there any known issues (other than no USB) for doing this?

            • 3. Re: PSoC 5 clock questions
              user_1377889

              Worx.

                 

               

                 

              Bob

              • 4. Re: PSoC 5 clock questions
                user_78878863

                I just tested whether I can configure that together. There is an example project 'SAR_SPIM_USB' that uses both the SAr ADC and USB. By default it uses an external crystal. I disabled the crystal, configured the IMO to 24MHz and the PLL to 36MHz.

                   

                Funny enough, the error message says:

                   

                ADD: sdb.M0059: error: Error in component: ADC_SAR_0. Internal clock frequency value must be between 1 MHz + 0.25% (1.0025 MHz) and 18 MHz - 0.25% (17.955 MHz).

                   

                I would like to see how to fulfill that requirement :) (And even when the PLL uses a crystal as source, the project doesn't build)

                   

                (Edit: my mistake, see below for what went wrong)

                • 5. Re: PSoC 5 clock questions
                  user_78878863

                  @bob: that project configures 944444 sps, to 1Msps.

                     

                  We actually had this discussion before: http://www.cypress.com/?app=forum&id=4749&rID=82366 but it seems that bug has not be fixed :(

                  • 6. Re: PSoC 5 clock questions
                    user_1377889

                    @Hli

                       

                    There is no "bug". When you can guarantee that with your environment setting (clocks) the required 18MHz is not exceeded (which will NOT be the case when using the free-running IMO) the project will build.

                       

                    So your choice is to use an external X-tal which - as you tell Creator - has 0% tolerance. This project will build.

                       

                     

                       

                    Can you please explain what you mean with your post "that project configures 944444 sps, to 1Msps."

                       

                     

                       

                    Bob

                    • 7. Re: PSoC 5 clock questions
                      user_463759797

                       When I ran across that issue of clock tolerance, I simply unchecked the tolerance requirement in the GUI, and it built.

                         

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                      I don't know if this is a bug or not.  I found it peculiar, but also a work around, so it did not bother me. 

                      • 8. Re: PSoC 5 clock questions
                        user_78878863

                        As I said - i also tested with the XTAL as clock source, and the same problems happens. I even told Creator I have a 18MHz crystal (with 0% tolerance even), and used the XTAL as direct clocksource, and the project did not build. (Edit: my mistake, see below for what went wrong)

                           

                        To your project: I downloaded it, unzipped it, and opened it in Creator 3.1. In the schematic the clock for the ADC is set to 17MHz, and the SAR ADC says its running with 944444sps. Maybe you want to check again?

                        • 9. Re: PSoC 5 clock questions
                          user_78878863

                          Oh, the error in may test was:

                             

                          ADD: sdb.M0059: error: Error in component: ADC_SAR_0. Internal clock frequency value must be between 1 MHz + 0% (1.0 MHz) and 18 MHz - 0% (18.0 MHz).

                             

                          Quite strange, maybe its because I had in on the IMO before?

                          • 10. Re: PSoC 5 clock questions
                            user_78878863

                            Oh, the problem was before the computer, no inside. The SAR_SPIM_USB example project has two SAR ADC. I did set one to 1Msps, but attached the 18MHz clock to the other one :(

                               

                            Its still a strange error message, but it happens only when the internal clock is used. I don't know why Creator cannot figure out by itself that there is a proper clock available.

                            • 11. Re: PSoC 5 clock questions
                              james.fry

                              It's because the internal clock + it's maximum uncertainty is > than the maximum clock input for the ADC at 1Msps.