9 Replies Latest reply on May 19, 2014 12:39 PM by alastair.robinson

    Verilog problem

    alastair.robinson

      Hi,

         

      I'm a newcomer to PSOC, and have been playing around with a CY8CKIT-049 board.  I have a few projects in mind where these devices will be ideal - but I've hit a snag with a verilog component.

         

      I've attached the simplest project possible which shows the problem - but in short, I have three inputs to my custom component.  A signal is mutiplexed to one of two input signals according to the state of a third, and then the output (a bidir pin) is set either to 1'bz or 1'b0 according to the state of the multiplexed signal.

         

      It's easier to express in verilog than English - and looks like this:

         

      wire output_signal_out;
      assign output_signal_out = sel ? input_signal : input2;
      assign output_signal = (output_signal_out ? 1'bZ : 1'b0);

         

       

         

      When I compile it, however, I get the following message in the "output" tab:

         

      ERROR: BiDirTest.vh2(40,4) : Unexpected token '!'. Expected '<=', or ':'
      ERROR: BiDirTest.vh2(43,2) : Unexpected token 'Net_2'. Expected '<=', or ':'

         

       

         

      Looking at the VH2 file, the offending lines are:

         

      IF !(\component01_1:output_signal_out\) THEN
          Net_2 <=  ('0') ;
      ELSE
          Net_2 <= 'Z';
      END IF;

         

       

         

      Any ideas?  Have I been unlucky enough to hit a compiler bug on my first project?  Or am I doing something wrong?