Easiest approach will be to use a timer that counts on a given internal frequency. The capture input of the timer will save the actual count which you can read-out in a connected interrupt where you reset the timer again.
When using two of these construct you are able to measure both the high-time and low-time of your signal.
Something like this ? D produces a high pulse = period width of PWM inout, its ISR
reads and resets counter.
Set capture on - edge, with ISR enabled in component, capture width
of PWM high time when ISR fires and capture register read.
Resolution clk show = 1 uS measurement resolution, 16 bit counter
can count a period up to ~65K us.
I think you can replace D and its inverter with a T F-F, just did not look at this.
One mod, move PeriodISR to falling edge of period indicator from D, eg. the output
of inverter / data input to D.
hello Dana , i need the PWM measurement too. I will give your schematic a try, but i miss some detail info about the proper Counter configutration.
maybe you even have this as little creator project at hand to share. b.r. Markus
I have a project, but not working. Seems interrupts not working the way
I wanted, so stumped at the moment, and today have other commitments
so cannot work on it.
The project is PSOC 3 based, runing on -030 board, so you would have to
change device, and should compile into PSOC 5 OK, or so I think.
Note I fixed all re-entrant errors in project, so on PSOC 3 compiles w / no
errors or warnings.
thanks Dana for sharing your project.
i did porting to kit LP050 and some code workaround (and both ISR).
but results are still not the way i want. :-(
i have no possiblity to change PeriodISR to falling edge as mentioned.
the result i want to get for lcd is:1st line: D.C.xx.yy %
2ndline : Frequency:xx.yy kHz
can you pimp my projectcode for doing so ?
my test signal is TTL 1.02kHz fixed frequency and 0.01 to 99.90% variable duty cycle
from a 2D-rotation hallsensor(360° in 12bit-PWM_angle resolution).
need the correct duty-cylcle value for further calculations of position-change speed..
The period ISR taken off the D output, then inverted, is effectively falling
edge, end of the period. The D high time, or its low time for that matter, either width, is =
period of the input signal. So you set the period ISR to rising edge, the D and inverter
take care of the rest.
Attached is a basic project you can modify to suit your needs. Measures pulse width
and duty cycle. It does this not on every input cycle as it is not a pure HW approach
and I chose to do it with one timer. With two timers you could do it on a per cycle basis,
or use Verilog for an optimal; solution.
Where are you located? I live near Bremen, Germany
I live near Augsburg and work in Kaufbeuren (Allgäu).
greetz from southern Bavaria. Markus
hello dear dana,
thank you for sharing your simplified project. As it works fine on PSoC5LP so far, I like to port your latest Creator-project to
PSoC4000 ( CY8C4013SXI-410) device for having a very small and low-cost solution for wanted flow-meter application comunicating via I2C to host device (PSoC3 based).
unfortunately there is no logic inside the small PSoC400 device, so i consider to use external inverter
and two pins for inputig the PWM-test signal.
best regards Markus
You may use a CY8C4245xxx which you can get for $1 at this time in single quantities and that chip includes some logic.