1. To double ADC_SAR sampling rate, clock second ADC though NOT element. This way two ADCs will work in counterphase. The drawback is that no two ADCs are the same (offset/slope/INL), which will cause few bits resolution loss. Another way of ADC overclocking was reported by "kabron", which also leads to lower resolution (charge pump may be the cause). http://www.cypress.com/forum/psoc-5-device-programming/adc-sar-overclocking-technique So both ways data rate will be increased at expense of resolution. If data received is known to be true sine, increasing sampling rate yuilds no extra information about the data. Having 16 samples per period at lower resolution (~8-bit) is worse than 8 s/period @12-bit. 2. Let me simplify my understanding of the setup. The PSoC is working as (kind of) analog transciver: ADC samples 120kHz (ultrasound) signal at 1 MHz into RAM buffer, and then unloads acquired data in slow motion through analog interface to external equipment using DAC8 (at what rate?) Having only 8 sampled points per period is marginal and recorded waveform doesn't look pretty. But if output is passed through analog reconstruction filter, the resulting wave will look smooth and have 12-bit resolution. The filter has to be high-order (4+) to make it look sine-like, but 8 points per period is sufficient to reconstruct the wave (video uses TI mf4cn-100 4th order filter): https://youtu.be/2S8i9v-lD_M Unfortunately, PSoC has only 8-bit DAC, so the output wave resolution still will be limited to 8 bits (even though output wave will look nicer). Here DAC output rate comes in play. If relatively slow, then PSoC's one of the derivative DACs with higher resolution may help (DV_DAC, etc). http://www.cypress.com/documentation/application-notes/an64275-psoc-3-and-psoc-5lp-getting-more-resolution-8-bit-dacs This way a smooth output with resolution of 9-10 bits can be achieved, but the limiting factor is still DAC, not ADC's sampling rate. If output rate is really slow, PWM DAC may give better resolution. My first suggestion would be: (I) add external analog reconstruction filter, (ii) change VDAC8 to DV_DAC. It all changes if DAC required output rate is high (>10-20kHz), because of PSoC5 DAC issue (bit-flipping glitch). At those rates it's resolution drops down to ~6-bit, something to consider. PSoC analog coprocessor may better suited for this task, having switched cap filter and 13-bit DAC. http://www.cypress.com/products/psoc-analog-coprocessor 3. I believe that it is possible to interpolate data between sampled points using PSoC5 Digital Filter component, by feeding it's input with sampled data interleaved with either zeros or original data (a1, 0, a2, 0....) or (a1,a1, a2,a2,...). The Filter needs to be set to some high-order , e.g. Butterworth 7th, and should be placed between RAM and DAC. At low output rate it can be handled by CPU.
The output frequency is around 20khz, (160,000 samples per second through the DAC). Based on the AN6425, it looks like using iDAC's in parallel would be best. The dithering is too slow by 20, and the ADC feedback is snail's pace (100 samples per second).
I looked on Google and could not find the Bit Flipping issue mentioned anywhere. What is that glitch, and where can I read more on it?
If I invert the clock signal to the ADC's, then I should only be 1/18mhz off between the two samples. I would expect to need a 9 clock sample delay between the two ADC's. The bit resolution loss might be acceptable. I suspect I could create a counter to delay the startup clock into the second ADC, but I want to try the easier stuff first.
I like the analog filter idea. I will look into it also.
I'm starting to understand the interpolation methods. The website at the end of the sentence helps. It explains some of the arcane terms better than I've seen before. I'm just curious how fast cosine is on the PSOC. I'll find out. http://paulbourke.net/miscellaneous/interpolation/
I'll look into the Digital Filter. That sounds promising.
At high output speed (>200 ks/sec) PSoC5 DAC shows spikes (like on picture below) every time code flips bits xxxx1111<->xxxx0000 (16 times while going from 0 to 255). At about >1Ms the noise is unbearable. Voltage output close to Vss is also saging, distorting output. Compared to PSoC5, PSoC4M DAC is better in this regards (both 8-bit).
To have 2 ADC_SAR working out-of-phase, drive samplig using soc terminal with 1MHz clock (use NOT element for ADC_2)
For analog output filtering look e.g into 8-order LTC1064-2, all it needs is a clock provided by PSoC.
Standard math sin() calculation on PSoC5 takes >1500 CPU ticks. With 12-bit sine lookup table I get ~56 ticks. At 64 MHz BUS_CLOCK and 160ks/sec all you have only 400 ticks for interpolation. It is unlikely that PSoC can make 6 multiplications on the fly that fast. Cubic interpolation is about same result. I would try Digital Filter first - it is free (no coding...)
Laslty, I have feeling that the task does not fit well for PSoC (need 2-3x faster ADC, >320kB memory to store data, and 12-bit DAC, etc.) Would it be easyer to upgrade to e.g. M4 micro?
Thank you for the information. I think I've seen that issue with the bit flip, but due to other parameters in the system it is filtered out by the time the receiver gets it. We got lucky. Several thousand feet of wire between us and the receiver helps dramatically.
I was able to use the digital filter block, and you are correct. It does indeed do what I needed, and works well. The output amplitude drops off dramatically, but I think we can compensate.
In addition, the DAC being unsigned causes issues when paired with the signed digital filter. That causes wrap from top to bottom when using full 0-255 values for the ADC input 8 bit into the filter. Very interesting phenomenom.
We only have to deal with 2 millisecond bursts of information, and have several tens of milliseconds to process the wave form. Regardless, the DFB provides good interpolation for free.
You are right about the cpu choice. But, when the project started several years ago, it was the best low cost solution. We are doing something new, and the toolbox provided by the PSOC has more than compensated for its short comings, even with the bit flip issue. (We avoided a bullet on this one)
I think I understand what you are talking about now on the ADC interleave.
I have been working on a jitter in acquisition of +/- 1 microsecond. So I switched my ADC to a logic controlled hard Start Of Aquisition (SOC). In that case, you would indeed use a NOT on the 1 mhz acquisition trigger clock.
Until I needed to control the jitter, I was using software start, and the signal creation started on cue due to logic.
I apologize for my previous answer. You are right, no need to delay the base clock, simply sync to the base clock and flip the 1mhz acquisition start signal.