2 Replies Latest reply on Jun 9, 2017 8:51 AM by content.librarian

    Reset Input on CRC Component


      Does anyone know what the Reset input on the CRC component (V2.40) is supposed to do?  On page 2 of the data sheet I find the sentence "The reset input defines the signal to synchronous reset the CRC."  In the Component Changes section under version 2.0 an item reads "Asynchronous input signal reset is added."  However, it doesn't actually say what is reset.  Also, it contradicts itself (synchronous vs. asynchronous).


      I had assumed that the reset line would either clear the seed/CRC register or load the seed value (which is 0 in my case), but it doesn't seem to do that.  I assert and de-assert the reset input before clocking in new data.  The first CRC is always correct, but subsequent CRCs are wrong.  However, if I write a zero to the seed register in software before the 2nd and subsequent data streams, the CRCs are always correct.  Thus, I believe the seed/CRC register is not getting reset by the Reset input.


      Since the data sheet doesn't really tell what the Reset input does, I don't know if this is expected behavior or an undocumented "feature".  Does anyone know?



        • 1. Re: Reset Input on CRC Component

          The reset input defines the signal to synchronous reset the CRC.That is correct.


          "Asynchronous input signal reset is added" is there for earlier version 2.0 .

          • 2. Re: Reset Input on CRC Component

            OK.  Thanks for the info.


            I did some experimentation.  To get it to reset, I had to hold BOTH Enable AND Reset high long enough for a clock to occur (actually, I held them high for a couple of clock cycles).  So, it appears that the Reset is synchronous.  I wasn't clear (to me, at least) from the data sheet that Enable had to be high in order for reset to work.  Perhaps some clarification in the next revision of the data sheet might be in order.  Anyway, it's working now.