1 Reply Latest reply on Jul 7, 2016 4:06 AM by content.librarian

    FX3 Slave FIFO 32-bit won't work: AN65974

    apelsinapa_1597131

      We've just got started testing the FX3 (CYUSB3014-BZXI) on a custom board, connected to a FPGA as in the AN65974: Designing with the EZ-USB® FX3™ Slave FIFO Interface.
      With the SlaveFifoSync example configured at 16 bits and a 100 Mhz PCLK, the cypress streamer application recieves data at 179000KB/s. Then when the firmware is changed with the CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT = 1 nothing works.

         

      The FPGA is a configured with the state machine from the provided vhdl code.

         

      FLAGA/FLAGB is inactive, so the fpga remains in idle mode - transfer never starts. All FX3 init code checks out without any errors, new GPIF design for 32-bit with GPIF2 designer don't seem to work either.

         

      We're obviously missing something...?

         

      (Meanwhile we'll continue search the forums for similar problems - no exact match found yet)