I use very low PCLK frequency (less than 100Hz). I could not find in the FX3 technical reference what the minimum GPIF II external PCLK can be.
Is there a minim PCLK frequency, when the GPIF II is in slave, synchronous mode, with externally provided clock? What is that minimum?
I also tried sync mode with internal clock (9.6 and 12 MHz) - similar results. The first time the flag is asserted 3 clock cycles after the buffer is full. But for the second buffer it is asserted in 1 cycle.
I thought maybe the clock frequency is too low - KBA210733 (Configuring EZ-USB® FX3™ GPIF-II DLL) lists 10MHz as a minimum, while other FX3 documents do not list a minimum clock frequency. Using 12 Mhz clock I still do not see consistent DMA_Ready behavior.
Am I missing something? Anyone?