1 Reply Latest reply on Mar 6, 2017 9:16 AM by content.librarian

    FX3 DMA_Ready flag - delay inconsistent

    content.librarian

      Hi,

         

      I am trying to test how the DMA_Ready flag works. For that I use a very simple interface and state machine, that would allow me to monitor the flag. See the attached GPIF designer screenshots for the interface and the state machine.

         

      I have setup with a DMA channel from the GPIF to USB, in auto mode. The channel uses 2 buffers, each with size 16 bytes.

         

      The GPIF clock is provided externally, using the positive clock edge.

         

      On the attached waveform snapshot, cursor A indicates the point when WR goes low. After that there are 4 clock cycles that read 4 32 bit words (16 bytes), and on the third positive clock edge the DMA_Ready flag goes low.

         

      Cursor C is when the DMA_Ready goes high again, after the socket has switched to the second buffer. 4 more words are clocked in, and then on the first positive clock edge the DMA_Ready goes low. There is not 3 clock cycles delay this time - only one. Why? Is this normal?

         

      Thank you,

         

      Dimitar

        • 1. Re: FX3 DMA_Ready flag - delay inconsistent
          content.librarian

          I use very low PCLK frequency (less than 100Hz). I could not find in the FX3 technical reference what the minimum GPIF II external PCLK can be.

             

          Is there a minim PCLK frequency, when the GPIF II is in slave, synchronous mode, with externally provided clock? What is that minimum?

             

           

             

          Thank you,

             

          Dimitar

          • 2. Re: FX3 DMA_Ready flag - delay inconsistent
            content.librarian

            I also tried sync mode with internal clock (9.6 and 12 MHz) - similar results. The first time the flag is asserted 3 clock cycles after the buffer is full. But for the second buffer it is asserted in 1 cycle.

               

            I thought maybe the clock frequency is too low - KBA210733 (Configuring EZ-USB® FX3™ GPIF-II DLL) lists 10MHz as a minimum, while other FX3 documents do not list a minimum clock frequency. Using 12 Mhz clock I still do not see consistent DMA_Ready behavior.

               

            Am I missing something? Anyone?

               

            Thank you,

               

            Dimitar