It is possible to have more than 16 inputs to an ADC in a CY8C24x94 device, using the Mux bus. An example project for the same is available in the below link.
But 10ksps throughput is not possible per channel. An 8 bit incremental ADCINC has a maximum speed of 6.5ksps. That would translate to around 400 samples per second per channel. So, if speed is critical, I think PSoC3 or PSoC5 would be the best choice.
If speed is cruicial as mentioned by ganesh, PSoC3/PSoC5 is worth a try. The ADC in PSoC3 gives a maximum sampling rate of 384 ksps for 8 bit resolution. Analog MUX available in PSoC3 can be used to multiplex cahnnels easily and achieve the necessary 10ksps sample rate per channel.
Acually 385ksps would be for a singl channel in the continous mode. Because of the pipe-line nature og the decimator inside the ADC, the sample rate is about 1/4rh of that.
Thanks for the replies! So it seems I could get 6khz per channel with 16 channels using the psoc3?- that seems fine. What I was hoping to do is use 16 input pins with up to 16 muxed to an ADC. Not all pins would require this speed (they could be sampled less frequently), and some at times might be disabled or connected to capsense, or made as a digital IO.
With the device I am building I want to use the PSOC's flexibility to acomodate a couple simple passive input modules that would use the same pins but with various modes as to their operation. I would want to change this configuration dynamically in code rather than at programming time.
I was about ready to abandon my design due to the PSOC 5 with the SAR not being in production yet, but PSOC 3 might just work.
This gives me another question, looking at the PSoC® 3: CY8C32 datasheet, page 47: I can't tell if there are 16 pins that could route to the ADC or the capsense, it doesn't seem so.
I actually realized that I don't need nearly that many inputs, and my questions in my last post I'm not attempting at this point.
I have been working with that code provided above and it works very well. After the reading I have done it seems as if the incremental ADC is among the slowest available on the psoc 1. Your calculation of 400 sps at 16 channels assumes the incremental ADC. What would be the performance if I was to use the SAR or Delta Sigma? I need only about 5 channels now but I need a minimum 2ksps.
Also, doesn't the 24x94 have less analog/digital blocks than some of the others?, I would imagine I could have more than 1 incremental ADC's running with a different chip.
I realize the need to wait for stabalization with the delta sigma, and the lack of sample and hold for the SAR, but can something be done to work around this and get say 3ksps * 5 channels? From what I can estimate I can, but my tests don't give me stable results.
If you need to measure only 5 signals, then I would suggest you use CY8C29466 and the TriADC. A TriADC can convert 3 inputs simultaneously. You can convert all the 5 signals in two ADC cycles. That will give you a very good throughput.
However, a TriADC cannot be placed in CY8C24x94 device as it has only two analog columns. You could try the DualADC in the CY8C24x94, which can measure two signals at the same time. With a DualADC, you can measure all 5 channels in 3 ADC cycles.
Thanks for your replies. I have a CY8C29466 with the TriADC that seems to work before multiplexing, it even appears to work up to about 12khz. After reading your page on this topic : http://www.planetpsoc.com/psoc1-kb-analog/30-changing-the-inputs-to-an-incremental-adc.html I am attempting what you call option 1 to maximize my sample rate, however I seem to be having issues with interfering values. In the asm file for the triADC_INT I call code to switch the mux, and then waste 1us (everything high power) for settling. I specifically have my call at the user code region that says "a good place to switch mux", which is after the counters, and integrators are stopped, the counters restarted, but before the integrators are restarted. I am assuming that I must need to call this before the counters are started (not in the user code section), or before the counters are stopped in the first place.
Any ideas on my problem, or suspicions?
How are you synchronizing the foreground and background processes? How are you tracking which inputs are measured by the ADC in the foreground process?
When you switch the input in the user code area, the result of the previous conversion is already stored in the ADC result variables. So, there should be no interference. Also, you say you are providing a delay of 1uS for settling? Where are you providing this delay?
In my opinion, option-3 should also work fine for you.
1. Set Input1, Input2 and Input3 to the TriADC channels 1, 2 and 3
3. Wait for data ready
4. Read Result1, Result2 and Result3
5. Set Input4 and Input5 to the TriADC channels 1 and 2
7. Read Result4 and Result5
8. Repeat from step 1
The PSoC Hacker
Thanks for the reply. When you say "processes" I think you are refering to synchronizing my code with the asynchronous interrupt ADC code. I am using a very simple lock to prevent the interupt from corrupting my data, in the worst cast throwing out a sample. I realized that I actually was locking in the wrong place allowing for the data to be corrupted in certain cases, I should hopefully be able to make this work now if this is the only problem.
Also, you mention:
however, if you look at TRIADC8.h there is no number of samples argument like the single channel ADCINC void TRIADC8_1_GetSamples(void);Thanks for your help,
Use the TriADC instead of TriADC8. The TriADC8 is a simplified version of TriADC and does not have the flexibility of TriADC. Use the TriADC user module and set the resolution to 8 bits. You can do single sample conversion using this user module.
The PSoC Hacker
I am interested in this post. With the PsoC 1 how can I make a sample and hold amp. I am trying to capture a slow moving analog signal then 1 mS later sample the same signal again for a voltage spike. Do I need an external samle and hold amp?
Forget my email. It was an easy answer after all.