4 Replies Latest reply on May 2, 2014 5:55 AM by mudabir.kabir.a

    Question about AN87216 - GPIF™ II Master Interface

    content.librarian

      Hi, I have read through the document of the application note AN87216 - Designing a GPIF™ II Master Interface, but I still cannot figure out the purpose of the GPIF data counter and address counter. They are set as 2048 for data counter and 256 for address counter. I am guessing the counter values are based on DMA buffer configurations, but what is the connection between these configurations? In the master GPIF state machine, what is the purpose of WR_DATA_WAIT and RD_DATA_WAIT states?

         

       

         

      Regards,

         

      C.H. Chen

        • 1. Re: Question about AN87216 - GPIF™ II Master Interface
          mudabir.kabir.a

           Hi C.H.Chen

             

                 Lets say you have 32 bit interface between FX3 Master and Slave. And Slave has DMA buffer size of 1K bytes each and 8 such buffers.

             

          The purpose of address and data counter is to introduce flow control and prevent data loss,.

             

          The Address and data counter ( They are just 2 counters and names dont matter) in master keeps track of how many bytes of data have actually been written to the Slave. Every DR_DATA in gpif state machine will send out 32 bits of data ( 4 bytes) and then Address and data counters are incremented by 1. When address counter reaches 256 ( 256 x4 = 1K bytes), It means that a buffer in Slave has been filled completely. There is a delay is Slave switching to next buffer. The master should ensure that it doesnt drive data during this buffer switching ( usually few microseconds). WR_DATA_WAIT is just a state where address_counter is reset to 0 and this takes enough time to ensure that  the Slave has switch to next buffer. 

             

          Similarly data counter is loaded with 2048 ( for 8K buffer, 2048x4 bytes). When data counter value hits, you have written to all 8 buffers in slave, you go back to RD_WR_IDLE , reload the counter to 0 and check flag B ( which tells if Slave has any buffer freed or not) and accordingly drive data. 

             

          Hope this helps

             

           

             

          Regards

             

          Mudabir Kabir

          • 2. Re: Question about AN87216 - GPIF™ II Master Interface
            chun-huai.chen

             Thank you very much for the clear explanation. It's very helpful.

               

            So the WR_DATA_WAIT deals with buffer switching delay on SLAVE side and the IN_DATA_WAIT state deals with the delay on MASTER side, is that right?

               

            When EZ-USB FX3 is sending out the data, there is also this kind of delay when sender is switching between its buffers, right?

               

             

               

            Regards,

               

            C.H. Chen

            • 3. Re: Question about AN87216 - GPIF™ II Master Interface
              mudabir.kabir.a

               Hi C.H. Chen,

                 

                     Yes, your understanding is right.

                 

               

                 

              Regards

                 

              Mudabir Kabir

              • 4. Re: Question about AN87216 - GPIF™ II Master Interface
                mudabir.kabir.a

                 When the master is driving data to the slave which inturn is stored in slave buffers, Master has to take care of buffer switching delay in the slave and not drive any data during this time. Likewise, when the slave is driving data to the master, master should ensure slave doesn't drive data ( controlled using SLRD and SLOE) when master is switching to its next empty buffer before reading further data.

                   

                 

                   

                Regards

                   

                Mudabir Kabir