Look at the Verilog for the Count7 component ("c:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\Count7_v1_0\Count7_v1_0.v" ):
The output is called 'count', not 'cnt'. So your line needs to be
hli, thanks for the reply. While I'm sure you know more about PSoC than I ever will, I respectfully disagree. The autogenerated verilog from the UDB editor instantiates Count7_v1_0 with 'cnt'. (I think correctlly.) From the file you mentioned (thanks for that path), its output is 'cnt' not 'count'. Perhaps your eye was caught by the lower instantiation of Counter7 which does use 'count'?
Do you agree the autogenerated Count7_v1_0 Count7_1 call was correct?
I don't fully undersand the cy_psoc3_count7 line. Especially the .cy_period(7'b1111111). I'm targetting PSoC5LP. Is that a problem?
input wire clock,
input wire en,
input wire load,
input wire reset,
output wire [6:0] cnt,
output wire tc
/* Hardware parameters */
parameter EnableSignal = 1'b0;
parameter LoadSignal = 1'b0;
cy_psoc3_count7 #(.cy_period(7'b1111111), .cy_route_ld(LoadSignal), .cy_route_en(EnableSignal))
/* input */ .clock(clock), /* Clock */
/* input */ .reset(reset), /* Reset */
/* input */ .load(load), /* Load signal used if cy_route_ld = TRUE */
/* input */ .enable(en), /* Enable signal used if cy_route_en = TRUE */
/* output [6:0] */ .count(cnt), /* Counter value output */
/* output */ .tc(tc) /* Terminal Count output */
The "cy_psoc3" is just a historical remnant (yes, there have been times without a PSoC5!). The UDBs of a PSoC3 and a PSoC5 are quite the same, so they never changed that name.
Ah, now I think I know what you actually mean. I thought the error you mentioned was in how to instance the internal counter7 component, but its about using the public Count7 component, right?
I think you should post the code you are using to use the Count7 component. You cannot directly access its internal signals, but need to bind them to signals you have in your outer component (just like how in the snippet you post the counter7.count is bound to the 'count' parameter of the Count7 component. Just concatenating the names of component and parameter doesn't work...
I found a post in Stackoverflow that might be useful: https://stackoverflow.com/questions/20066850/verilog-how-to-instantiate-a-module
Silly me, it took me another read to see that you are using the UDB editor... So maybe you can describe where you actually want to use the signal (screenhots maybe?)
Did you try to use Count7_1.count (I see this syntax in the generated file for startup values)?
Apart from that, when I understand the component auth guide right (in part 4.3.4) you need to use Verilog to access the counter7 component.
Thanks to you both, hli and Bob.
I was hoping to decode the cnt value to make complex periodic waveforms and staged triggers. I was shy about using verilog, because I was enjoying the autogenerated APIs and verilog files. It's so much easier to read than write!
For now, I'm using the drag-and-drop Count7_v1_0 schematic component which I can route into my decoder. Eventually I'll step up and write it in verilog.
Right now I'm embattled in another module. Work, work, work.
Did you try using the regular Count7 component? It has all the connections you need. Or do you use the DataPath for your decoder?
(Maybe you upload your project here - 'File / Create Workspace Bundle', so we can have a look at what you are doing)
Hi, I am hitting myself with same issue. Using the UDB editor and trying to use the Count7 component with Creator (v3.3 and v 4.1), there seems to be no clean way to use the counter current value. It looks like Count7 configuration dialog is missing the counter current value output configuration and therefore is hitting with the error. When error is reported, no verilog is generated. Verilog seems to have everything needed. The details are like described in the old posts. Sadly this will reduce the usability a lot for implementation of simple asynchronous shift register with synchronisation signals.
You can get help more easiily when you post your actual project so that we all can have a look at all of your settings. To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.
Hi, Bob !
Thank you for attention. I created very simple project with Creator v4.1 that demonstrates what is happening and attached it. The condition with "Count7_1_count" is failing. When replacing the condition with "1'b1" the generated verilog will have Count7_1_count wire defined under wire and register declarations.
wire [6:0] Count7_1_count;