2 Replies Latest reply on May 19, 2017 9:09 AM by content.librarian

    SPIS_WriteTxDataZero() and FIFO in SPI Slave

    content.librarian

      Hi,

         

      I'm trying to implement an 8-bit SPI slave on PSoC 3/5 and use the 4-byte hardware FIFO.  According to the data sheet, since I have CPHA==0, I must write directly to the shift register using SPIS_WriteTxDataZero() for the first outgoing byte.  How does this operation affect the FIFO?  In other words, if I have an empty Tx FIFO and then write via SPIS_WriteTxDataZero(), is the FIFO still empty?  If so, can I fill it up using 4 SPIS_WriteTxData() operations before the first data clock edge is even received?