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The analog reference power and analog buffer power are only valid for devices with full function analog. For the 21434, if you call CSD_Stop, it should turn off all the analog and digital blocks and the power will now only be from the CPU running. Use the following logic.
1. Turn On CSD
2. Initialize baselines
3. Initialize finger threshold
4. Start I2C
5. Switch Off CSD
6. Wait for command from I2C
7. Start CSD
8. Scan sensors
9. Update baseline, process button press etc
10. Go to 5
But remember, the baseline update will track environmental changes only when the baseline is updated regularly.
thanks for your advise.
it only reduce 0.5mA,
maybe i lost something?
What is the total current? Even though all the resources are stopped, the CPU itself will consume some current depending on the frequency.
Can you try the following,
1) Wake up every 64 Hz, using the Sleep Interval.
2) Enable I2C
3) Start CapSense
4) Scan capsense once
5) Stop CapSense, disable all blocks power
6) Disable I2C and its interrupt
7) Enable the GPIO interrupt (on attention line)
8) goto sleep
For I2C, have one dedicated pin as Interrupt pin (Attention pin). When the master makes this pin low, come out of sleep, Enable I2C and keep on scanning (don't go to sleep, untill this pin is High).
The only restriction would be that the master has to make this Attention line Low before sending any I2C commands.
I will try to give you an example project on this method. Please give me 3-4 days time.
My solution (IMO=6MHz, CPU_SPEED=SYS_CLK/256, and CSD_Stop)
make current down to 1.8mA from 4.3mA,
but it lost I2C command often.
I try to request more resouce, like pre-start bit or two times wake up command,
to make this case easily.
Thanks for your check list,
I will try it.
Ganesh and Narayana, you are so kindly, thanks a lot.
SysClk/256 at a SysClk of 6MHz, is too slow for the CPU. You will definitely miss the I2C data at this CPU speed. What you have to do is when an I2C command starts coming in, you should switch the CPU frequency to a higher value to SysClk/1 or SysClk/2. After stopping the CSD and before configuring the CPU clock to SysClk/256, enable rising edge interrupt on the I2C line. When I2C transaction occurs, a GPIO interrupt will also occur. Inside the GPIO interrupt, set the CPU clock to SysClk/1, and disable the GPIO interrupt. When you want to go back to low power mode, change the CPU clock to SysClk/256 and again enable the GPIO interrupt.
Here is a project that implements sleep and CSD. This may be useful to you.
I have modified the previous attached project to achieve minimum sleep current (3uA).
modification: The drive mode of Rb pin is set to High-Z Analog before PSoC goes to sleep so that Rb resistor does not consume any current during sleep.
Hope this project will help you.