3 Replies Latest reply on Apr 9, 2010 1:33 PM by abhijeethimmatraou_

    Power Down mode in MoBL SRAM

              I am using a CY62157ESL MoBL SRAM connected to a Xilinx Virtex-5 FPGA. There will be a power down condition when the FPGA is not powered and the SRAM is powered by 2.5V. I need to have a very low, known current draw by the SRAM in this mode. I am buffering the CE_N pin to ensure a VCC level. What should I do with the other pins. The data sheet implies they all need to be at the VSS or VCC rails, so do I need to use a resistor at each pin to ensure this. I could put 60K resistors to the FPGA 2.5V, which would pull down the pins in the power down mode. What is recommended?   
        • 1. Re: Power Down mode in MoBL SRAM
                  Hi Carl,   
          CY62157ESL has a wide voltage range: 2.2V - 3.6V and 4.5V - 5.5V. If you are operating the device in 2.2V - 3.6V range and powering up the SRAM through a battery when the power is down, you need to connect Only chip enable(CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.   
          Let me know if you need any further help.   
          • 2. Re: Power Down mode in MoBL SRAM
                    I will drive CE_N to VCC and use the 60K resistors to pull BHE_N and BLE_N to VSS (GND). I believe the load on the other pins will look like a diode to GND. I assume this is OK if leaving them floating is OK.   
            • 3. Re: Power Down mode in MoBL SRAM
              Use of supervisory chips is what Cypress recommends. Having pull up/ pull down resistors is ok but not recommended. I am attaching an app note below which is aimed at addressing exact same issue that is bothering you. Have a look and then let me know if you have any more doubts.