You can implement two SPI Masters using PSoC devices that have more than 1 digital block row, like CY8C27x43, CY8C29x66 etc. In these devices, you can use a digital communication block to place an SPIM user module and route the SPI signals through the Row Output / Row Input nets and the Global In and Global Out nets to the desired GPIO pins.
In addition to the PSoC 1 devices that Graa mentioned above, PSoC 3 and PSoC 5 devices can create an SPI interface in their universal digital blocks (UDBs).
So all PSoC 3 and PSoC 5 devices could support multiple SPI interfaces via the UDBs.
There are 4 8-bit digital blocks per row in PSoC 1 parts, and two of them them are communication type blocks (DCx) that can be configured as SPIM, SPIS, UART Tx/Rx, and the other two are basic function blocks (DBx) that can be configured as PWM, counter, PRS, etc.
So you can get 1 x SPIM and 1x SPIS from each row of the digital blocks.
CY8C21x34, CY24x94, CY8C27x43, CY8C28xxx, and CY8C29x66 all support SPIM and SPIS. The new CY8C28xxx family also support various length SPI (8~16 bit) in user modules.