I think this could be done in the hardware using the UDBs. Do you need the processor's MIPS to perform other functions (and thus the desire to offload to the hardware) or are you just curious if it can do it? Reason I ask is if you already have code, it seems like it would be an easy port if you keep it done in software.
Thanks for the reply. You have piqued my interest with talk about UDBs - that's something I think I'll need to learn more about.
I ported my existing code (From a Rabbit 5000 uP) over and have it working. I placed a single digital input pin, enabled interrupt on falling edge and popped a simple loop polling the pin for state into the ISR. It feels like a really inefficient way to do it on a PLD hence why I'm wondering about whether it can be done in hardware.
One thing I was very impressed with was this: I connected a 'not' gate to a digital output pin and connected it to a LED on the board and it continued to work even when the debugger was sitting on a break point. For someone who is brand new to PSoC and CPLDs this was impressive. ;-)
Now, is there a good resource I can dig into to learn about the capabilities of the UDBs?
I had a look at the timer v1.0 component.
It looks like it could do the job, partly, when set to trigger on either-edge. However it's fifo can hold a maximum of only 4 counts. If that could be uprated to a higher number, like say, 48 then it would be ideal.
I'll take a look at that. :-)
The Components have a Hardware FIFO which is 4 Bytes deep. The size of the FIFO can be increased beyond this too. For this, the SRAM memory will be used up, and ISRs will handle to ensure that the bytes are stored in the FIFO of specified length.