Did you check the Design Wide Resources file to see if anything in the clocking tree changed with the update?
I thought I remembered hearing someone had a problem because one of the clock settings got altered during the update as the tool deemed the old setting no longer valid.
Thanks for the quick reply, Bobby, I will investigate...
UART component has 4 bytes of hardware FIFO. Since you are using 12 bytes of data as a packet, there is a an ISR running under the hood which takes care of handling the interrupt. The extra buffer size (greater than 4) is implemented in the RAM available.
You can try out the following methods to get the communication working:
1) Since ISR is used, try increasing the BUS clock to 12MHZ or 24MHz (in case it was initially set to 3MHz) in the clocking tree. This will make handling of ISR's faster.
2) Using the APIs which use Blocking method of transmission is helpful when packets of data are being transmitted. This eliminates the need for Delays in between the data bytes.
Let us know if it works.