
1. Re: PSoC 3 DS ADC Clipping
content.librarian Sep 20, 2011 5:23 AM (in response to userc_44193)Hi Jonathan,
The 16bit ADC in +/1.024V exactly behaves this way:
gives 0x0000 for 0V input,
0x7FFF for 1.024V input
and saturates at 0x917D for a 1.136V input.
If you limit your input to < 1.024V, you'll never get output greater than 0X7FFF and a 16bit variable will just do the job for you. If your input goes higher than 1.024V by any chance, then there is a problem, the ADC outputs a count greater than 0x7FFF and you will interpret it as a negative voltage when actually it was not.
In single ended mode(01.024V) too, we have the same problem. We can trasfer the values through DMA into a UDB datapath and perform saturation arithmetic. But, it'll be an advanced concept for you to implement yourself.
I'd suggest you to limit your input or use the 15bit ADC. Note that the 15bit ADC can be configured to sample data at rates equal to 16bit ADC, though the maximum sample rate of 15bit ADC is higher than 16bit ADC.
If you prefer using the saturation logic, please file a cypress tech support case.
Regards,
Pfz