Writing just Verilog code will implement the combination or sequential logic using the PLDs available in UDB.
However, the Datapath available in UDB can be utilized by using the Datapath Tool. This is much more powerful way of using the UDBs as Datapath has an ALU of it's own which can do 8 arithmetic and logical operations. A datapath has FIFO, Accumulator and Data Register. Apart from this, there are also hardware comparators which will compare the value of the Accumulator with Data Regsiters. This works in parallel with the main core (8051 / ARM Cortex M3 of PSoC 3/5), thereby improving the utilization of the available digital resources.
I can use the datapath to add two bytes together using the ALU.
But I can also add two bytes using Verilog, can't I ?
Is there a disadvantage to doing it in Verilog?
Is there an advantage to doing it in the datapath?
The difference is size. An implementation of a PMW in verilog would take up most of the available logic. With a datapath it is only a single block.
The ALU conbined with a state machine makes a small little processor.
In PSoC1, it was decided to not have programmable logic other than the LUTs on the analog columns and digtal output rows. That was because we could not afford the space programmable logic would require. Remeber FPGAs sell for as much as 10 times the cost of a PSoC1. We thought we had most microcontroller peripherials covered until about the second week PSoC went into production someone asked from a quad shaft decodered. (damn!)
On PSoC3/5 it was decided that we could never cover all the perepherial that you guys wanted and that programmable logic was required. The designers didn;t want the overhead that FPGAs would require. The data path is a good compromise.
You have to remember that the microprocessor was originally desgned to make logic design easiler. Back in the early 70s, digital design was either SSI chips or a custom chip. With the rapid increase of digital designs it became apparrent that there would not be enough digital engineer to to the work. The solution was a programable sequencal logic device or a micro-processor. If I remember correctly, Intel would give them away for free if yyou bought your ROM and RAm from them.
I will admit that the dath paths are my favorite part of PSoC3/5 and I am consider an analog guy.
Dave Van Ess
Also the datapath configurations are held in SRAM tha is in the CPU memory space. With the power of the CPU, DMA , and the wide bandwith of the memory space you now have a dynamicly configured system. The results of this will not be fully explored for at least 5 more years. Guys! you are being given an oppertunity to do things no one else has done before. Time allocatable hardware. 200%- 300% utilization of hardware. Neuro type designs. The ideas are linitless. Remainds me when people asked why they should use PALs went 74HC chips cost 9 cents.
You are being offered to the chance to define how logic is designed in the future. Hell, the tools to do this haven't even been written yet!
Dave Van Ess
That was a great answer! So you could do all of those ALU functions in Verilog, but it would use much more hardware that if you just used a datapath.
I guess that's doubly true (or octally true) because the datapath can cover 8 functions in a single block.
Thanks. Great article.
So, in fact, you could probably turn them into special purpose CPUs if you wanted?
Yes. The way I like to view it is to count the number of "processors" in PSoC:
CPU, DMAC, DFB, + 24 datapaths = 27. But we're not done yet:
State machines in PLDs, number is limited only by available UDB resources. But we're still not done:
Processing can also be done in the analog domain, e.g. using a SC/CT block in mixer mode to do analog multiplication.
So I usually state that we have 27+ "processors" in PSoC 3/5, and so don't just use the CPU like one would in traditional MCUs.
Back in the day we used to make analog computers with op amps. With four stand alone and four CT-SC block opamps, that makes eight more.
PSoC Rocks my friends!