The SAR consists of built-in hard- and software. The clock frequency written in the datasheet is the analog column clock divided by four. The name in the datasheet is fclock, which is given as column clock / 4. The dependency of the cpu-clock has to do with the way the SAR works, it stalls the CPU while each conversion step is made to get accurate results.So (as I read the datasheet) with an analog clock rate of 1.3 MHz you'll get a sample time of about 20µs. @5V, 24 MHz.Bob
Thank you for answering. But I still have some doubts abut SAR6.
Although I call the SAR6_cGetSample() function serveral times (for example in a bucle), the sample only will be obtained when the CPU is released, and it will be when the Conversion Time (aprox.) has passed. So, the way to change the Sample Rate is changing the Conversion Time (Sample Rate = 1/Conversion Time ¿?) through the Analog Column Clock (Conv. Time = 6 * Period of(Analog Column Clock / 4)), is it correct?
You are right with your assumptions. Sample rate = 1 / Conversion time. The GetSample() function waits until the conversion is made (blocking). Unlike ADCINC there is no way to initiate a conversion and look for a result ready a bit later.
Why do you want to increase the conversion time? Yes, of course you may reduce/adjust the column clock at your needs, there is a lower limit for the analog column clock at about 125 kHz.
Ok, I get it.
I don't want to increase the Conversion Time, my question was only in order to understand how it works, because in my project I will have to change the Sample Rate to get different results and to compare them.
Thanks for your patience.
May I ask why you are using the SAR6?
It doesn;t have a sample/hodd in front of it. and when you trigger it, it holds the CPU clock for 24 Column clock cycles. That's right, the CPU is stalled during that time. For a 1MHz column clock that would be 24usec. This could seriously mess up other User Modules that rely on fast response for interrupts.
If it is sample speed, we can make a DelSig ADC to do 60Ksps @ 8 bits with a 50% cpu loading. (We haven't released the new DelSig yet but hold on!) I could do 6 bits at 125ksps but the CPU loading is close to 100%
Dave Van Ess
I know that a S&H in front of the SAR6 is needed, which is mandatory for fast signals but not for slow, I think.
Regarding to the CPU held, I want to use the SAR6 with an UART and a DAC modules altogether. The UART is responding quite well but about the DAC I haven't yet implemented it. If I have problems with the CPU response I will try to increment the Sample Rate of the SAR6 in order to decrease the Conversion Time and consequently the CPU response time.
The reason why I use this converter in front of the other is that my project guidelines says it because the objective is to compare results obtained from different converters, for example the 50/60 Hz interference rejection or noise.
I really appreciate your comments about the special characteristics of this converter.