I presume AMUX 1 is being used to mux both Vx's and Ix's as you have the TIA input
coming from it.
Also is there not a problem that AMUX1 output sits at Vref due to fdbk around TIA ?
Eg. TIA is a follower to Vref, which puts its inv input at 2.5 ?
Should have mentioned this in the first post, the TIA is being used as an inverting op amp when its muxed in. The external pin will be connected to a resistive sensor and then to ground, so that node being pulled to vref is drawing a current according to the change in resistance.
Then why not eliminate OpAmp and AMUX2 and just add an input to AMUX1 for the TIA ?
Or if using TIA with several, but not all, AMUX1 inputs, just eliminate OpAmp, no need
for it, as it contributes more drift and offset error.
I cant get rid of the Opamp, it wont compile without a block there. It errors when I have a mux common connected diirectly to any other amux. I need to be able to connect any of the 8 inputs to the TIA. Think i have just settled on using two SARs instead of using a single SAR.
You need not waste a unity gain PGA because of ther error you are facing by connecting the output of one AMUX to another.
Here is an easy way to get rid of it.
1. Break the connection between the output of AMUX_1 and AMUX_2.
2. Place a "Net Tie" component between the two. Now, the "Net Tie" component would act as a mediator between the output of AMUX_1 and the input of AMUX_2.
3. Place a net constraint component on the wire between AMUX_1's output and the net tie component and select its configuration to AMUXBUSL.
4. Similarly, place a net constraint component on the wire between net tie component and AMUX_2's input and select its configuration to be AMUXBUSR.
5. Now if you build the project, you will not face any error.
For further reference, I have attached a screenshot of how the "TopDesign.cysch" would look.
AMUX_solution.png 44.3 K