It might be advisable to consider the effects a 100 mFD capacitor has
discharging thru output parasitic diode when Vdd falls to ground. Thats the
only discharge path C has and its thru a very small area (junction) diode.
And of course 100 mFD cap has a lot of charge in it, and potentially very
low ESR, read high currents result.
There is another issue with such high C load.
The OA stability may have been analyzed with output routed
directly to a pin. But if we employ routes thru muxes and other
components, out to a pin, then hang 100 mfd off pin, and take our
feedback from the pin, we have added a lot of phase shift due to
route R, and stability and phase margin will rapidly decline.
Useful reference - http://electronicdesign.com/power/what-s-all-capacitive-loading-stuff-anyhow