2 Replies Latest reply on Nov 14, 2014 1:00 PM by content.librarian

    [FX2] Packet data missing/twice

    content.librarian

      Hi,

         

      I'd like to use the slave FIFO to push some data from a device to my host. I configured my FX2 chip to use EP6 as IN endpoint. However if I try to read some data on my host, the data is completely mixed up (missing or occurs multiple times, however there is no random data i.e. all data was generated by my device).

         

      My configuration:

         
       REVCTL = 0x03;  SYNCDELAY;    PORTACFG = 0x00;  SYNCDELAY;   IOA = 0x00;  OEA = 0b10000000; // Enable A7 output  SYNCDELAY;    CPUCS = 0x12; // 48MHz CPU clock, CLKOUT enable  SYNCDELAY;    // I/O mode + clock  IFCONFIG = 0x03; // external clock, synchronous (slave FIFO)  SYNCDELAY;    EP2CFG = 0b10100000 // EP2: Valid, Out, Bulk, 512B, Double  SYNCDELAY;  EP4CFG = 0x00; // off  SYNCDELAY;  EP6CFG = (2 << 0) | (2 << 4) | (1 << 6) | (1 << 7); // EP6: Double, Bulk, In, Valid  SYNCDELAY;  EP8CFG = 0x00; // off  SYNCDELAY;    // do a fifo reset  FIFORESET = 0x80;  SYNCDELAY;  FIFORESET = 0x02;  SYNCDELAY;  FIFORESET = 0x04;  SYNCDELAY;  FIFORESET = 0x06;  SYNCDELAY;  FIFORESET = 0x08;  SYNCDELAY;  FIFORESET = 0x00;  SYNCDELAY;        EP2FIFOCFG = (1 << 0); // EP2: 16-bit  SYNCDELAY;    EP4FIFOCFG = 0x00; // set 8bit to enable PORT D  SYNCDELAY;    EP6FIFOCFG = (1 << 0) | (1 << 2) | (1 << 3); // EP6: 16-bit, ZEROLENIN, Auto Commit In  SYNCDELAY;    EP8FIFOCFG = 0x00; // set 8bit to enable PORT D  SYNCDELAY;    // 'prime the pump' see REVCTL, OUTPKTEND  OUTPKTEND = 0x82;  SYNCDELAY;  OUTPKTEND = 0x82;  SYNCDELAY;    PINFLAGSAB = 0x64;   // flag B: EP6PF, flag A: EP2PF  SYNCDELAY;  PINFLAGSCD = 0x08; // flag C: EP2EF  SYNCDELAY;    EP2FIFOPFH = 0x80; // DECIS=1, PKTSTAT=0, PKTS=0, PFC=0  SYNCDELAY;  EP2FIFOPFL = 0x04; // PFC += 4  SYNCDELAY;    // EP6: flag high if >= 1p + (512-32)B in fifo  // 512 - 32 = 480 = 0x01E0 = 256 + 224  EP6FIFOPFH = 0b10001001; // DECIS=1, PKTSTAT=0, PKTS=1, PFC=256  SYNCDELAY;  EP6FIFOPFL = 0xe0; // PFC += 224  SYNCDELAY;    // PA7 / FLAGD as port A 7, not fifo flag + chip select  PORTACFG = 0x00;  SYNCDELAY;    // all fifo control pins lowactive  FIFOPINPOLAR = 0x00;  SYNCDELAY;    // AUTOIN len limit  EP6AUTOINLENH = 0x02; // 512  SYNCDELAY;  EP6AUTOINLENL = 0x00; // + 0  SYNCDELAY;    // PORT D as inputs:  OED = 0x00;  SYNCDELAY;
         

       

         

      Pseudo-code on my device:

         
            
      • Wait until FlagB = 0
      •     
      • Send a 16-bit word
      •     
      • Repeat
      •    
         

      Is there any configuration issue? Or do I have to check my FIFO interface timing?

         

      Thank you for your support!

         

       

         

      Kind regards,

         

      Peter