7 Replies Latest reply on Dec 29, 2014 3:56 PM by user_14586677

    Shadow Register Basics

    content.librarian

      My understanding of shadow registers is a little lacking and I've come up with some questions that I think will help clarify them for me.  In the pdf for AN2094, a scenario is given in which the input pin will be permanently latched high. 

         

      Why does writing a '1' to P0[1] permanently set it high?

         
            
      • Is there an actual voltage being put on the pin?
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      • Can the input only be set permanently for 'resistive pull up' or 'resistive pull down'?
             
                
        • I can't see how this could be the case for 'high z'
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      •     
      • Would 'resistive pull up' be in danger of latching high and 'resistive pull down' be in danger of latching low, or would they both be in danger of latching either way?
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      The other thing that is confusing me is why using a shadow register bypasses this problem?  From the example, '1' is written to P0[1] which causes it to latch permanently.  I don't see why performing the following statements differs in results:

         
          Port_0_Data_SHADE |= 0x01;   
         
          PRT0DR = Port_0_Data_SHADE;   
         

      vs.

         
          PRT0DR |= 0x01; // Set P0[0]   
         

       

         

      The difference that I can see is that one sets PRT0DR via a 'copy' machine instruction while the other does it using an 'or' machine instruction.  Would this make a difference in the latching?

        • 1. Re: Shadow Register Basics
          user_1377889

          Welcome in the forum!

             

          In PSoC1 when reading a digital pin the actual voltage on the pin is taken and interpreted as either low (0) or high (1).

             

          Now take for instance that to the pin an LED is connected which lowers the output down to 1.7V which will be interpreted as low (0). Reading the pin, inverting the red value and writing that back to the pin will not yield the result wanted. This is the classic read-modify-write cycle that may lead to an error or rather to an unexpected behaveour.

             

          This is the point where a shadow-register drops in: all reads are done using the register, all writes at first alter the register which then is written to the port. So the above shown read-modify-write cycle will give the expected result.

             

          There are other scenarios despite from the LED as you have already seen, but that one is (at least for me) quite understandable.

             

          In PSoC 3,4 and 5 different IO-paths for reading and writing do not need shadow registers.

             

           

             

          Bob

          • 2. Re: Shadow Register Basics
            user_14586677

            This might be useful -

               

             

               

                

               

                          

               

                      

               

            https://www.youtube.com/watch?v=tei6q5M3C0g     Part 2 (discusses shadow regs)

               

             

               

            https://www.youtube.com/watch?v=Dt8Kv_uHGD4    Part 1

               

             

               

             

               

            Regards, Dana.

            • 3. Re: Shadow Register Basics
              content.librarian

              Thanks for the responses! 

                 

               

                 

              So, I think that I understand why the input latching symptom happens.  The input path and output path block diagrams seemed to help a lot.  From those I realized that the "pull up" and "pull down" drive modes have both an input path and output path (makes sense for something like I2C where you could have the data line being written to or read from).  Based on this, it makes sense that any pin mode with an input and output path could have this "latching input" problem.  If an output is written to this pin, it will affect the voltage on the input path and may cause a false reading depending on what is externally connected to the pin.  This would imply that the "high z" drive mode would not have this problem because it has no connection to the output path.  Is this correct?

                 

               

                 

              Moving on to the actuall use of shadow registers.  The difference that I see in using shadow registers vs. not using them is that, when using them PRTxDR is modified with a COPY command and when not using them it is modified with a bitwise AND/OR.  It still doesn't make sense to me why using COPY wouldn't write to the output path while a bitwise AND/OR would write to the output path.

                 

               

                 

              At this point it would be nice to understand this last part, but not necessary to get things to work.

              • 4. Re: Shadow Register Basics
                user_1377889

                Both, the COPY and the bitwisw AND are writing to the output path. The difference is: the latter (and) first has to READ from the pin, while the COPY reads from the shadow register.

                   

                 

                   

                Bob

                • 5. Re: Shadow Register Basics
                  content.librarian

                  Ahhhhh, yep that makes more sense. Thanks again for the help.

                  • 6. Re: Shadow Register Basics
                    user_1377889

                    You are always welcome!

                       

                     

                       

                    Bob

                    • 7. Re: Shadow Register Basics
                      user_14586677

                      You are always welcome!

                         

                       

                         

                      Dana.