Looks tedious, eg. looking at schematic. It would take a lot
of hacking, and you would loose program/debug, but you could
run the 5LP at 1.8 V. Looking at schematic there are a lot of
zero ohm R's in the power paths you could remove. I took
a cursory look at it, there may be other gotchas.
Try filing a CASE, maybe factory has done this another way -
To create a technical case at Cypress -
“Create a Case”
You have to be registered on Cypress web site first.
I don't think I could deal with losing my program and debug ability, I will file a case like you sugested. Off the top of your head, can you think of anything that I should be aware of about the PSoC when I am running it at 1.8V instead of 3.3V? Programming? Certian in-active devices?
I also have never designed a board with a jtag to program a chip with, I have the data sheet for working with the jtag, but I am still aperhensive. When is a boot loaded needed? I read that it is needed when you boot from flash, but isn't the code memory always read from flash? I am a little confused still.
Bootloading is a method to have the PSoC updated in the field without using any extraneous hardware programmer. Simple USB connection to a PC satisfies the requirements, a software is already provided by Cypress. The PSoC has to be pre-programmed with a BootLoader firmware that allows for this kind of update.
Simplest reliable programmer is the MiniProg3 for your self-designed PCBs. It still maintains debugging capabilities and can of course be used to program that bootloader I was talking about.
You may run a PSoC in two different power-supply modes:
Regulated and unregulated. You cannot easily switch between these modes since some connections for Vcc are different.
Have a look into the family datasheet and search for "unregulated".
Since 1.8V is the border voltage between regulated and unregulated you may try to run unregulated which will work from 1.8 to 5V without any changes.
If you really committed to modifying a PSoS board, I suggest to try a schmartboard first:
There is not many components on the PCB, you may need to replace one drop-down regulator.
Thanks for the information! Continuing down the line of thought around the boot loader and using the min program 3 from cypress, what all would I need to do program the board? I would need to have a header exposing the correct pins, and I would need to use the software from cypress to load the binary onto the microcontroller.
I am not certain if you meant programming using jtag requires the use of the boot loader block in the psoc creator software, or if it is somehow added onto the binary automatically when the programming software is used, or if it is not required at all when using JTAG.
Your information on regulated and non regulated variants of the PSoC was very helpful too! Any other suggestions about designing a board with a PSoC are more than welcome! In my case size, weight, and power must all be minimized.
Also, thanks for the schmart board sugestion too!
Concerning PSoC programming:
On your Kit-050 a programmer is already integrated using a seperate Cypress chip. When you start to design your own boards an integrated programmer is a bit overdone since you only need a 5-pin header for a MiniProg3 to program your board. This would probably take less space than an additional chip plus interface plug (USB). The software needed is only Cypress Programmer which will send a hex-file to your board using USB <-> MiniProg3 <-> PSoC. The SWD interface uses the same pins, so debugging is still possible.
Using a bootloader requires initial programming that has to be done like mentioned before. At the price of a some flash space for the bootloader and a micro-USB socket you have the ability to update your project in the field by some trained user. You may even provide your own update-software, I think Cypress has released the C# source for Windows.
I see, the bootloader is so that the board can be easily programmed via USB, that helps a lot! I think for my application, at least for now, being able to program the board over JTAG will be more than sufficent.
Thank you everyone for the help!
When you run any design at LV your noise margin becomes a greater
challenge. Board layout, bypassing, noise all issues to be concerned with.
http://www.cypress.com/?rID=39677 AN57821 - PSoC® 3, PSoC 4, and PSoC 5LP Mixed Signal Circuit Board Layout Considerations
http://www.cypress.com/?rID=40247 AN58827 - PSoC® 3 and PSoC 5LP Internal Analog Routing Considerations
http://www.cypress.com/?rID=39974 AN58304 - PSoC® 3 and PSoC 5LP – Pin Selection for Analog Designs
http://www.cypress.com/?rID=50230 AN68272 UART BL PSOC 3, 4, 5LP
http://www.cypress.com/?rID=41002 AN60317 I2C BL PSOC 3, 5LP
http://www.cypress.com/?rID=57561 AN73503 USB HID BL with GUI Host PSOC 3, 5LP
http://www.cypress.com/?rID=56014 PSoC® 3, PSoC 4, and PSoC 5LP Introduction To Bootloaders
http://www.cypress.com/?rID=83293 AN86526 - PSoC® 4 I2C Bootloader
http://www.cypress.com/?rID=50230 AN68272 - PSoC® 3, PSoC 4 and PSoC 5LP UART Bootloader
Device Programming -
www.cypress.com/?rID=57435 AN73054 - PSoC® 3 and PSoC 5LP Programming Using an External Microcontroller (HSSP)
http://www.cypress.com/?rID=44327 PSoC® 3 Device Programming Specifications (CY8C32xxx, CY8C34xxx, CY8C36xxx, CY8C38xxx CY8CTMA39x, CY8CTMA8xx, CY8CTMA6xx)
http://www.cypress.com/?rID=72883 PSoC 5LP Device Programming Specification