I did modify the example given in slaveFIFO2b_streamIN.v (attached) to be able to send the stream of bytes packed into 32 bit words (using Xilinx FIFO core). Quite naturally the SLWR now doesn't stay low all the time, but goes high when FIFO output is not valid.
Unfortunately after this modification once FLAGB goes low it stays low forever.
To reproduce it I did modify the test bench fpga_master_tb.v (attached) to simulate the FX3 behavior to the best of my understanding.
From what I see if FLAGB goes low, but I don't write enough words to fill entire DMA buffer, the DMA will not get flushed.
Do I understand correctly that I have only two options:
Otherwise FLAGB will stay low forever.
The FPGA code is developed and fixed to demonstrate the Slave FIFO interface of FX3.
We don't have any expertise on FPGA.
Let us know if there is any query/issue on FX3 side.