2 Replies Latest reply on Jul 12, 2017 8:08 PM by kelvinxu_2593591

    Build a co-processor in UDB with Verilog in PSOC 5LP?

    kelvinxu_2593591

      Hi, 

         

      I am looking for example designs which uses the UDB in 5LP to work closely with the CPU. 

         

      I need to write 32b data to UDB and read from result from the UDB. My verilog in UDB will do some custom computation. The closest I saw on the Cypress is the fan control but it uses functions like FanController_GetActualSpeed, is that an API or do I have access to the source codes? 

         

      Are there any ref designs which uses the registers in UDB like memory mapped registers? 

         

      Thank you!