0 Replies Latest reply on Aug 13, 2008 2:45 AM by haub.michael

    SPIS documentation not correct

      my app:   
      - PSoC doing CSD as its main task   
      - communication to master via SPIS   
      - SPIS switched of during CSD   
      (because sales man from cypress says irq from SPIS may corrupt CSD sample)   
      - SPIS multiple bytes in each cycle (e.g. 4 bytes)   
      - SPIS using software SS   
      - SPIS irq not enabled, polling   
      - PSoC slave is only sending, not receiving   
      - clocks from SPI master in cyclic packets (for the multiple bytes)   
      - PSoC-slave may start listening to SPIS in the middle of a clock packet   
      and may therefore not be able to send all its multiple bytes out, so using timeouts   
      for first byte, for other each byte, for all bytes. If timeout occures speeping to   
      synchronize on next clock packet.   
      1. documentation says:   
      "On the falling edge of the Slave Select signal, the data is transferred from the Tx Buffer register to the Shift register."   
      Finding: SPIS_EnableSS() and SPIS_DisableSS() have no influence on when TX data buffer is transfered to shift register.   
      2. documentation says:   
      "Data to be transmitted to the SPI Master is written to the Tx Buffer register. This clears the Tx Buffer Empty status bit."   
      Finding: On first SPIS_SetupTxData(...) data is automaticaly/imediatetly transfered to shift register and TX_BUFFER_EMPTY flag is therefore set.   
      On second SPIS_SetupTxData(...) data stays in TX data buffer and TX_BUFFER_EMPTY flag is reset.   
      3. documentation says:   
      "SPIS_bReadStatus ... Side Effects: The status bits are cleared after this function is called."   
      Finding: SPIS_bReadStatus() has no influence on status bit TX_BUFFER_EMPTY.   
      I have a problem with 1. How can i controll when TX data buffer is transfered to shift register, by my selfe?   
      What is the difference of TX_BUFFER_EMPTY and SPI_COMPLETE flag?   
      documentation says:   
      "Choosing the second option, "TxComplete," delays the interrupt until the last bit is shifted out of the Shift register."   
      But shift register is automatically loaded from TX data buffer when every bit of it has been shifted out (SPI_COMPLETE will be signaled) and then also SPI_COMPLETE flag would be set, or?   
      How could i tell the SPIS state machine that it should ignore the data automaticaly transfered from TX data buffer and go directly to the state when shift register is empty?   
      I think software has too low influence on the state machine.   
      State machine is not documentet correctly/enough.   
      A state diagram would be very helpfull.   
      Best regards